SRAM Memory Diagnosis Test Circuit for Precise Error Location
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Solution Overview
Problem
Conventional SRAM test element group patterns fail to accurately determine the location of errors in SRAM cell transistors, leading to inefficiencies in semiconductor yield improvement and error detection.
Innovation Solution
A memory diagnosis test circuit with a memory core block, word line selector, bit line selector, and analog mode control unit, utilizing shift registers to select and monitor word lines and bit lines, and a sense amplifier unit to sense-amplify data, allowing for precise error detection in SRAM cells with fewer pads, facilitating easier integration into a scribe line region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional SRAM TEG pattern is used for error detection, then the test structure can be implemented with standard SRAM architecture, but the exact location of errors in cell transistors cannot be determined
Solution Approach 1:
The patent segments the SRAM cell into six distinct transistor nodes (first through sixth transistors) and implements separate test paths for each node. By dividing the error detection function into node-specific test sequences, the system can precisely identify which transistor is faulty without requiring a completely complex test architecture.
Solution Approach 2:
The patent introduces intermediary test circuits including test inverters, test NOR gates, and test NAND gates that act as mediators between the SRAM cell transistors and the external test signal sources. These intermediary elements enable systematic activation and monitoring of each transistor node, allowing precise error location while maintaining manageable test structure complexity.
2Measurement precision
If more pads are used for comprehensive error detection, then error detection accuracy improves, but integration into scribe line region becomes more difficult
Solution Approach 1:
The patent designs the test structure to serve multiple functions: it can detect errors in any of the six transistors, support both analog and digital test modes, and operate with a reduced set of pads. The test circuits are configured to multiplex functionality, allowing comprehensive error detection without requiring separate dedicated pads for each transistor, thereby facilitating easier integration into the scribe line region.
3Productivity
If conventional test patterns are used, then manufacturing process is simple, but semiconductor yield improvement is limited due to inability to identify specific transistor errors
Solution Approach 1:
The patent implements feedback mechanisms where the output signals from the test circuits are fed back to the test signal generation units. This feedback allows the system to adaptively identify which transistor node is faulty based on the response patterns, enabling precise error localization and thereby improving semiconductor yield by allowing targeted rework or identification of defective units.
Solution Approach 2:
The patent utilizes parameter changes in the test signals (switching between analog and digital modes, changing test signal amplitudes and frequencies) to elicit different responses from the SRAM cell transistors. By varying test parameters systematically, the system can distinguish between different transistor faults without requiring proportionally complex test circuitry, thus improving yield efficiency.
Data Source
AI summary
According to an example embodiment, a memory diagnosis test circuit may include a memory core block, a word line selector, a bit line selector, and/or an analog mode control unit. The memory core block may include a plurality of memory cells. The word line selector may be configured to select one of a plurality of word lines of the memory core block using a first shift register. The bit line selector may be configured to select one of a plurality of bit line pairs of the memory core block using a second shift register. The analog mode control unit may be configured to monitor data corresponding to the selected word line and bit line pair.