SRAM Array Mirror Layout for Better Exposure Patterning

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Solution Overview

Problem

Current SRAM architectures face challenges in producing desirable patterns as the gap of the exposure process decreases, making it difficult to enhance exposure quality.

Innovation Solution

A static random access memory (SRAM) array pattern is designed with a substrate divided into regions where each region contains an SRAM cell, with shared elements like contact plugs, simplifying the manufacturing process and reducing cell area by arranging SRAM cells in a 2×2 array with mirror patterns along a horizontal axis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the exposure process gap is decreased to improve manufacturing precision, then manufacturing precision is improved, but it becomes difficult to produce desirable patterns

Engineering Contradiction:
Improveexposure qualityVSAvoidpattern production difficulty
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies asymmetry by introducing dummy structures (dummy contact plugs, dummy word lines, dummy bit lines) that are strategically placed to create asymmetric compensation patterns. These dummy structures compensate for the exposure process gaps by filling in the pattern deficiencies, allowing the main SRAM cell patterns to be produced with desirable quality even when the exposure gap is reduced.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent uses copying by creating mirror image patterns of the SRAM cells. Each SRAM cell is copied and reflected across bit lines to form symmetric array structures. This copying approach ensures that pattern defects are distributed uniformly and can be compensated through the mirror symmetry, improving overall exposure quality.

Inventive Principle:
Principle #26Copying

2Area of stationary object

If SRAM cells are arranged in a shared element array to reduce cell area, then cell area is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvecell areaVSAvoidmanufacturing process complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent applies merging by combining multiple SRAM cell structures into a shared array where contact plugs, word lines, and bit lines are共用 (shared) among adjacent cells. The dummy structures are also merged into the same manufacturing layers as the functional structures, allowing simultaneous formation through the same fabrication processes. This merging reduces cell area while managing manufacturing complexity through unified process steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements universality by designing the dummy contact plugs and dummy word/bit lines to serve multiple functions: they act as both placeholders for exposure alignment and as functional interconnect structures. The same manufacturing processes that create functional contact plugs and wiring also create the dummy structures, eliminating the need for separate manufacturing steps and reducing overall process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230403837A1Static random access memory array pattern
Publication Date: 2023.12.14 UNITED MICROELECTRONICS CORP
  • US20230403837A1 patent drawing
  • US20230403837A1 patent drawing
  • US20230403837A1 patent drawing

AI summary

The invention provides a static random access memory (SRAM) array pattern, which comprises a substrate, a first region, a second region, a third region and a fourth region are defined on the substrate and arranged in an array, each region partially overlaps with the other three regions, and each region contains a SRAM cell, the layout of the SRAM cell in the first region is the same as that in the third region, the layout of the SRAM cell in the second region is the same as that in the fourth region, and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis.