SRAM Mode Control for Automatic Power Saving Without Processor Monitoring
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Solution Overview
Problem
Existing SRAM technologies impose a large processing load on processors due to the need for determining access and transitioning to power saving modes, which is inefficient and burdensome.
Innovation Solution
A control device with a first storage unit that requires no refreshing, a processor, a bus arbiter, and a control circuit that arbitrates access requests and controls mode transitions based on predetermined time periods, reducing the need for processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the processor determines whether the SRAM is accessed based on current flowing through the SRAM, then the SRAM can be switched to power saving mode, but a large processing load is imposed on the processor
Solution Approach 1:
The SRAM automatically determines its own access status by monitoring the current flowing through it, and autonomously transitions to power saving mode without processor intervention. This self-service mechanism eliminates the processing load on the processor while achieving energy savings through automatic mode switching based on detected access patterns.
2Reliability
If the processor continuously monitors access requests to the SRAM, then accurate control of mode transitions is achieved, but the processor efficiency decreases
Solution Approach 1:
The access monitoring function is extracted from the processor and implemented as a separate current detection mechanism directly associated with the SRAM. This extraction allows accurate mode control to be achieved through dedicated hardware monitoring while freeing the processor from continuous monitoring tasks, thereby maintaining reliability while improving processor efficiency.
3Loss of energy
If the SRAM transitions to power saving mode frequently, then power consumption is reduced, but the response time for access requests increases
Solution Approach 1:
The SRAM dynamically adjusts its operating mode based on real-time access patterns detected through current monitoring. The system transitions to power saving mode only when access requests are determined to be absent, and quickly returns to normal mode when access is detected. This dynamic adaptation optimizes the balance between power consumption reduction and access response time by making mode transitions conditional on actual usage patterns.
Data Source
AI summary
A control device includes a first storage unit that requires no refreshing and has volatility, a first processor configured to access the first storage unit, a bus arbiter configured to arbitrate an access request from the first processor, and a first control circuit configured to perform mode control for the first storage unit based on the access request received from the first processor via the bus arbiter, wherein the first control circuit instructs, when a time period during which the access request is not received exceeds a predetermined time period in a state where the first storage unit is under a normal mode, the first storage unit to transition from the normal mode to a power saving mode.