SRAM Read-Modify-Write Single Cycle Modulated Word Line
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Solution Overview
Problem
Existing SRAM circuits require multiple clock cycles and significant power consumption for read-modify-write operations, particularly when modifying count values in histogram data, due to external data modification circuits and multiple word line assertions.
Innovation Solution
The SRAM circuit performs the mathematical modify operation internally within the SRAM, eliminating the need for external data modification circuits and reducing power consumption by completing the read-modify-write operation in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external data modification circuits are used for read-modify-write operations, then the SRAM can perform data modification, but power consumption increases significantly due to data signal toggling
Solution Approach 1:
The patent merges the data modification function into the SRAM array itself by integrating adder circuits within the memory structure. This allows the SRAM to perform read-modify-write operations internally without requiring external data modification circuits, thereby reducing data signal toggling and power consumption while maintaining data modification capability
Solution Approach 2:
The patent introduces a modulated word line signal as an intermediary control mechanism that coordinates the simultaneous read and write operations within a single clock cycle. This modulation enables the SRAM to manage internal data flow and modification operations efficiently, reducing the need for external circuitry and associated power consumption
2Ease of operation
If multiple clock cycles are used for read-modify-write operations, then data modification can be performed externally, but the operation time increases
Solution Approach 1:
The patent combines the read, modify, and write operations into a single integrated process within the SRAM array. By merging these operations and executing them simultaneously in one clock cycle through internal adder circuits and modulated word line control, the patent eliminates the multi-cycle external operation sequence
Solution Approach 2:
The patent performs the data modification action preliminarily within the SRAM array before the write operation completes. The internal adder circuits prepare the modified data during the read phase, allowing the write operation to simply store the pre-computed result, thereby completing the entire read-modify-write sequence in a single clock cycle
3Ease of operation
If multiple word line assertions are used for read and write operations, then data can be accessed and modified, but power consumption increases due to bit line operations
Solution Approach 1:
The patent uses a modulated word line signal that periodically controls the timing of read and write operations within a single clock cycle. This periodic modulation allows the SRAM to perform both operations using the same word line assertion sequence, reducing the number of separate word line assertions and associated bit line operations required
Solution Approach 2:
The patent merges the word line control for read and write operations into a single modulated signal sequence. This unified control mechanism enables both operations to share the same word line assertion, reducing redundant bit line activations and lowering power consumption from bit line operations
Data Source
AI summary
A read-modify-write operation is performed, within a single cycle of a clock signal, by: decoding an address to select a word line of a memory; applying a word line signal at a first voltage level to the selected word line; reading a current data word from a data word location in the memory; reducing the word line signal from the first voltage level to the second voltage level; performing a mathematical modify operation internally within the memory on the current data word to generate a modified data word; increasing the word line signal from the second voltage level to the first voltage level; and writing the modified data word back to the location in the memory.