SRAM Multi-Cell Operations for High-Speed In-Memory Computing
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Solution Overview
Problem
The bus connection between CPUs and memory arrays acts as a bottleneck in data processing, particularly in big data and machine learning applications, due to the mismatch between CPU speed increases and bus speed improvements, leading to inefficient data reading and writing operations.
Innovation Solution
A multi-memory cell operator with a non-destructive memory array, activation unit, and multiple column decoder that enables concurrent multi-cell operations by activating multiple cells in a column to generate Boolean function outputs, precharging bit lines, and performing in-memory calculations, allowing for simultaneous reading and writing across multiple columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional single-cell memory operations are used, then the memory array structure remains simple, but the data processing speed is limited by bus bottleneck
Solution Approach 1:
The memory array is segmented into multiple independently operable columns, each capable of simultaneous read/write operations. This segmentation allows parallel data access across multiple columns, effectively increasing data processing speed without requiring complex inter-column coordination logic.
Solution Approach 2:
The memory cells are designed to perform multiple functions: traditional storage, Boolean logic operations (AND, OR, NOT), and arithmetic operations (addition, subtraction). This multi-functionality eliminates the need for separate logic circuits, increasing processing speed while maintaining relatively simple memory structure.
2Productivity
If multiple cells are activated simultaneously for parallel operations, then computation throughput increases, but bit line interference and operation reliability decrease
Solution Approach 1:
Different columns are assigned different operational modes (read, write, compute) based on local requirements. Each column can be independently configured, allowing simultaneous operations without mutual interference. This local differentiation maintains high reliability while enabling parallel throughput.
Solution Approach 2:
Control logic acts as an intermediary that coordinates column selections and operation types. This intermediary ensures that simultaneous operations in different columns do not interfere with each other, maintaining reliability while maximizing computational throughput through parallel execution.
3Loss of time
If in-memory computations are performed, then data movement between memory and CPU is reduced, but energy consumption during computation increases
Solution Approach 1:
Storage and computation functions are merged within the same memory array structure. Boolean logic and arithmetic operations are performed directly on stored data using the memory cells themselves, eliminating data transfer to external logic units. This reduces data transfer time while keeping computation energy consumption low by utilizing the existing memory cell transistors.
Data Source
AI summary
A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.