SRAM Multiplexing for Write Stability
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Solution Overview
Problem
Static random access memories (SRAMs) face stability issues during write operations due to semiconductor process variations, leading to static noise margin problems.
Innovation Solution
The implementation of multiplexing units coupled to the write bit lines and read bit lines, which apply opposite logic voltages when a memory cell is not selected for writing, and activate the write word line to ensure accurate logic state storage by maintaining the state of unselected memory cells during the write cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operations are performed in SRAM during normal operation, then data can be updated, but stability issues and static noise margin problems occur due to semiconductor process variations
Solution Approach 1:
The write operation is segmented into distinct phases: a preparation phase where the read word line is activated to establish stable reference voltages on the bit lines, followed by a write execution phase where the write word line is activated. This temporal segmentation allows the system to maintain stability during data updates by ensuring proper voltage conditions are established before the write operation commences.
Solution Approach 2:
Before the actual write operation is executed, the read word line is activated in advance to pre-charge the bit lines and establish stable voltage references. This preliminary action ensures that when the write word line is subsequently activated, the memory cell is in a stable state that is less susceptible to noise and process variations, thereby maintaining static noise margin stability during the write operation.
2Speed
If conventional write operations are used, then write speed can be achieved, but distortion of logic states in unselected memory cells occurs
Solution Approach 1:
The circuit applies different voltages to different bit lines based on their selection status. Selected bit lines receive write voltages to update data, while unselected bit lines maintain their existing voltages through the multiplexing units. This local differentiation ensures that only the intended memory cell is modified while other cells retain their logic states, preventing distortion without requiring slower write operations.
Solution Approach 2:
Multiplexing units are introduced as intermediary components between the write bit lines and the memory cells. These multiplexing units selectively connect write bit lines to memory cells based on the activated word line, ensuring that write operations are precisely targeted. This intermediary mechanism prevents unwanted voltage changes in unselected cells while maintaining fast write speeds for the selected cell.
3Reliability
If multiplexing units are added to control write operations, then stability and write accuracy improve, but device complexity increases
Solution Approach 1:
The multiplexing units serve multiple functions: they act as switches to select which memory cell receives the write operation, they maintain voltage levels on unselected bit lines, and they provide isolation between write and read operations. By consolidating these multiple functions into a single component, the design achieves improved write stability and accuracy without proportionally increasing overall device complexity.
Solution Approach 2:
The circuit combines the write bit line control and read bit line control into unified multiplexing units that manage both functions. By merging these control functions into single integrated components rather than separate circuits, the design reduces the overall complexity increase while still achieving the desired write operation stability and precision.
Data Source
AI summary
A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other.