Compact SRAM Cell via Stacked Nano-Sheet Transistors
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Solution Overview
Problem
Modern integrated circuits face challenges in reducing the area required for two-port SRAM cells without fundamental changes in fabrication processes, as existing transistors consume significant space due to their physical configurations.
Innovation Solution
The use of complementary nano-sheet/wire transistor devices, specifically forming stacked nano-sheet devices with P-type and N-type layers, pull-up, pull-down, and pass gate transistors, along with shared gate structures, to create a more compact SRAM cell configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar or FinFET transistors are used in SRAM cell layout, then the transistor can perform basic switching functions, but the cell area becomes large due to the physical configuration of the devices
Solution Approach 1:
The patent transitions from planar (2D) transistor configurations to vertically stacked 3D transistor structures. The stacked transistor device includes multiple channel regions arranged vertically with gate electrodes positioned between them, enabling three-dimensional utilization of space. This dimensional change allows the SRAM cell to fit within a smaller footprint area while maintaining the necessary transistor functionality for memory operations
Solution Approach 2:
The stacked transistor device embeds multiple channel regions and gate electrodes within each other in a vertical arrangement. The structure nests first and second channel regions with first and second gate electrodes positioned between them, creating a compact nested configuration that reduces the horizontal space required for each transistor, thereby reducing the overall SRAM cell area
2Area of moving object
If the number of transistors in the SRAM cell is reduced, then the cell area decreases, but the drive strength and functional integrity may be compromised
Solution Approach 1:
By stacking transistor channels vertically, the patent increases the effective channel width without increasing the horizontal footprint. The stacked configuration allows multiple channel regions to be stacked above each other, providing equivalent or enhanced drive strength compared to planar transistors while occupying less area, thus maintaining power/drive strength requirements with reduced cell size
Solution Approach 2:
The stacked transistor device merges multiple channel regions and gate electrodes into a single integrated vertical structure. This combining of multiple transistor elements into one stacked device allows the SRAM cell to achieve the necessary drive strength through the combined effect of stacked channels while reducing the total number of discrete transistor components and interconnects required
Data Source
AI summary
One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further includes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.