SRAM Bit Cells with Stacked Nanosheet Transistors
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Solution Overview
Problem
Current semiconductor device fabrication techniques for SRAM bit cells with complementary field-effect transistors face challenges in achieving efficient packing density and reduced leakage current, particularly in integrating nanosheet field-effect transistors within a compact layout.
Innovation Solution
The proposed solution involves a 6-transistor SRAM bit cell design with a one contacted (poly) pitch (1CPP) layout, utilizing shared gate electrodes and stacked nanosheet transistors to form complementary field-effect transistors, where the gate electrodes are arranged in a spaced configuration along a longitudinal axis, enabling a compact and efficient layout that reduces bit line capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet field-effect transistors are integrated in a compact layout to increase packing density, then packing density is improved, but leakage current increases
Solution Approach 1:
The patent transitions from planar transistor layouts to vertically stacked nanosheet transistors arranged in a three-dimensional configuration. Multiple nanosheet channels are stacked vertically between source and drain regions, with gate electrodes wrapping around all sides in a gate-all-around arrangement. This vertical stacking enables higher packing density while the gate-all-around structure provides superior electrostatic control that suppresses leakage current in the off-state.
Solution Approach 2:
The patent employs composite material structures including alternating layers of semiconductor materials (e.g., silicon nanosheet channels) and sacrificial materials (e.g., silicon-germanium). These composite layer stacks are etched selectively to release the nanosheet channels and form the gate-all-around structure. The use of different materials with complementary properties enables both high-density integration and effective leakage control.
2Use of energy by moving object
If gate electrodes are arranged in spaced configuration along longitudinal axis in 1CPP layout, then bit line capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The gate electrodes are segmented into discrete units spaced along the longitudinal axis rather than forming continuous structures. This segmentation reduces the total capacitance of the bit lines while the segmenteD gate electrodes can be selectively controlled. The spaced arrangement breaks up large capacitive structures into smaller units, reducing overall bit line capacitance and improving energy efficiency.
Solution Approach 2:
The gate electrodes are arranged in a one-contact-pitch layout where multiple gate electrodes share a common contact structure, utilizing the vertical dimension to accommodate the spaced arrangement. This three-dimensional gate electrode configuration reduces bit line capacitance while maintaining manufacturability through shared contact structures that simplify the fabrication process.
Data Source
AI summary
Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.