SRAM Negative Voltage Level Shifter for Write Margin
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Solution Overview
Problem
The development of static random access memory (SRAM) devices faces challenges due to increased distributions of basic process characteristics, leading to decreased stability and yield, as well as low integrity and capacity compared to dynamic random access memory (DRAM).
Innovation Solution
The implementation of an array of SRAM cells with a word line driver and column decoder, utilizing pass gate transistors and negative voltage level shifters to drive selected and unselected word lines and bit lines with positive and negative voltages during write operations, and applying negative voltages to improve write margin and sensing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative voltage is applied to unselected word lines and control terminals during write operations, then write margin and data stability are improved, but device complexity increases due to additional voltage level shifting circuits
Solution Approach 1:
The patent applies parameter changes by utilizing negative voltage levels on unselected word lines and control terminals during write operations. This voltage parameter modification enhances write margin by ensuring proper switching behavior of selection switches, while negative voltage on unselected lines prevents unintended activation. The approach directly addresses the technical contradiction by improving reliability through controlled voltage parameter changes.
Solution Approach 2:
The patent employs negative voltage as an intermediary mechanism to mediate between selected and unselected memory cells during write operations. By applying negative voltage to unselected word lines and control terminals, the invention creates a clear electrical distinction that prevents crosstalk and ensures precise cell selection, thereby improving write margin without requiring additional physical isolation structures.
2Reliability
If negative voltage is applied to prevent retention degradation in unselected cells, then data stability is improved, but power consumption increases
Solution Approach 1:
The patent utilizes parameter changes by applying negative voltage to unselected word lines and control terminals during write operations. This voltage parameter modification enhances write margin by ensuring proper switching behavior of selection switches, while negative voltage on unselected lines prevents unintended activation. The approach directly addresses the technical contradiction by improving reliability through controlled voltage parameter changes.
Data Source
AI summary
Integrated circuit memory devices include an array of static random access memory (SRAM) cells arranged as a plurality of columns of SRAM cells electrically coupled to corresponding plurality of pairs of bit lines and a plurality of rows of SRAM cells electrically coupled to a corresponding plurality of word lines. A word line driver and a column decoder are provided. The word line driver, which is electrically coupled to the plurality of word lines, is configured to drive a selected word line with a positive voltage and a plurality of unselected word lines with a negative voltage during an operation to write data into a selected one of the SRAM cells. The column decoder includes a plurality of pairs of selection switches therein, which are electrically coupled to corresponding ones of the plurality of pairs of bit lines. The column decoder is configured to drive control terminals of a first of the plurality of pairs of selection switches coupled to the selected one of the SRAM cells with positive voltages concurrently with driving control terminals of a second of the plurality of pairs of selection switches coupled to an unselected one of the SRAM cells with negative voltages during the operation to write data.