SRAM Neural Network Memory with DAC Weight Adjustment
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Solution Overview
Problem
Conventional neuronal computation elements used in neural networks, such as resistive RAM, magnetoresistive RAM, and phase change memory, are not symmetric and require analog inputs, making them difficult to control and less stable compared to static random-access memory (SRAM) devices.
Innovation Solution
Implementing a crossbar circuit with SRAM cells and a digital-to-analog converter (DAC) to receive outputs from SRAM cells, allowing for more stable and easier control of neuronal computation elements, with the DAC being configured as a resistor ladder or field effect transistor, enabling precise current flow and weight adjustments in neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional neuronal computation elements (resistive RAM, magnetoresistive RAM, phase change memory) are used, then neural network operations can be performed, but the system becomes difficult to control and less stable due to non-symmetric characteristics and analog input requirements
Solution Approach 1:
The patent replaces conventional analog-based neuronal computation elements with a digital SRAM-based system. The SRAM cells provide symmetric, digital storage that is easier to control, while the DAC converts digital outputs to analog signals for neural network operations. This substitution of the computation element architecture directly addresses the stability and control issues by using robust digital logic instead of fragile analog structures.
Solution Approach 2:
The patent introduces a digital-to-analog converter (DAC) as an intermediary component between the SRAM cells and the neural network computation. The DAC receives digital outputs from the SRAM cells and converts them to analog signals suitable for neural network operations. This intermediary resolves the contradiction by allowing the use of stable, controllable digital SRAM storage while still enabling the necessary analog computations through the DAC interface.
2Reliability
If SRAM cells with DAC are used, then stability and control are improved, but device complexity increases due to the additional DAC component and digital-to-analog conversion circuitry
Solution Approach 1:
The patent merges the SRAM cell array and DAC into an integrated crossbar circuit architecture where multiple SRAM cells are arranged in a grid pattern with shared word lines and bit lines. The DAC is integrated at the output of each SRAM cell or column, allowing parallel operation. This merging approach reduces overall system complexity by enabling simultaneous operations across multiple neurons through shared circuit resources, despite the added complexity of individual DAC components.
3Ease of operation
If digital inputs are used instead of analog inputs, then ease of control is improved, but manufacturing precision requirements increase for the DAC and circuit integration
Solution Approach 1:
The patent changes the input parameter representation from continuous analog values to discrete digital values. The SRAM cells store digital states (0 or 1) that represent weight values, and the DAC converts these discrete digital inputs to analog signals for neural network computation. This parameter change from analog to digital domain provides easier control through digital logic while the DAC handles the precision requirements through controlled quantization and conversion processes.
Data Source
AI summary
Weights of a neural network are initialized by programming a plurality of unit cells. A given one of the plurality of unit cells includes one or more static random-access memory cells and a digital to analog converter device. The digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells. An amount of error associated with the initialized weights is determined. The initialized weights are adjusted in response to the amount of error exceeding a threshold amount of error.