SRAM Non-Clamping Write Driver with Negative BL Assist
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Solution Overview
Problem
Conventional SRAM write drivers degrade the stability and read margins by driving both true and complement write-data lines to positive voltage during bit-masking operations, and the additional circuitry for negative BL Write-Assist increases write time and area requirements.
Innovation Solution
A non-clamping write driver circuit that does not drive both bitlines to positive voltages during bit-masking operations, combined with a negative BL Write-Assist circuit that reduces the voltage level and transistor size, improving stability and read margins while reducing chip area and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional write drivers drive both true and complement write-data lines to positive voltage during bit-masking operations, then the write driver can perform masking operations, but the stability margin of the bit cell and read margin are degraded
Solution Approach 1:
The patent extracts the harmful effect of driving both bitlines to positive voltage during masking operations by introducing a non-clamping write driver that prevents the complement write-data line from being driven to VDD when masking is active, thereby removing the source of instability while preserving masking functionality
Solution Approach 2:
The patent applies preliminary anti-action by using a masking control signal to preemptively prevent the complement write-data line from being driven to positive voltage during masking operations, counteracting the potential stability degradation before it occurs
2Reliability
If additional circuitry is added to provide negative BL Write-Assist, then the yield is improved, but the write time and chip area increase
Solution Approach 1:
The patent merges the negative BL Write-Assist functionality into the write driver circuit itself, combining what were previously separate circuits into a unified structure that shares transistors and control logic, thereby reducing the area overhead and write time penalty of the Write-Assist feature
Solution Approach 2:
The patent implements multi-functionality by designing the write driver to handle multiple operations (normal write, masking, and negative BL Write-Assist) using a single integrated circuit structure, allowing the same transistors to serve multiple purposes depending on control signals
3Reliability
If additional circuitry is added to provide negative BL Write-Assist, then the yield is improved, but the chip area increases
Solution Approach 1:
The patent merges the negative BL Write-Assist functionality into the write driver circuit itself, combining what were previously separate circuits into a unified structure that shares transistors and control logic, thereby reducing the area overhead and write time penalty of the Write-Assist feature
Data Source
AI summary
Various SRAM non-clamping write driver with write-assist are disclosed, including a write driver circuitry that does not clamp the Bitlines (BLs) during the write operations, and a negative BL Write-Assist (WA) circuit that provides a negative BL boost desirable for use with high-density bit cells. When used with memories other than those having high-density bit cells, the negative BL WA improves the minimum voltage (Vmin) and frequency of operation.