SRAM and NVM Direct Interface with Pitch-Matched Column Logic
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Solution Overview
Problem
Existing data processing systems face inefficiencies due to the need for SRAM and non-volatile memory to share a system bus, leading to bus congestion and increased surface area requirements, as SRAM cells typically consist of more transistors than non-volatile memory cells.
Innovation Solution
A direct interface is established between SRAM and non-volatile memory, allowing data transfer without involving the system bus, with column logic controlling access and pitch matching to optimize layout, enabling burst accesses and efficient use of integrated circuit space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If SRAM and non-volatile memory are coupled to the system bus using a bus interface circuit, then data transfer between memories is enabled, but bus congestion occurs and system productivity decreases
Solution Approach 1:
The patent segments the memory interface by creating a dedicated direct interface circuit between SRAM and non-volatile memory, separating it from the main system bus. This allows memory-to-memory transfers to occur independently without blocking bus operations, thus resolving the bus congestion problem while maintaining data transfer capability.
2Reliability
If SRAM cells include at least six transistors to ensure proper operation, then reliability is improved, but the surface area occupied by SRAM array increases significantly compared to non-volatile memory array
Solution Approach 1:
The patent merges the SRAM array and non-volatile memory array into a unified memory system with shared column logic and pitch-matched layout. This integration allows the larger SRAM cells to be efficiently packed alongside non-volatile memory cells, optimizing the overall area usage while maintaining the six-transistor SRAM cell structure for reliability.
3Ease of operation
If the bus is used for memory access and data transfer, then ease of operation is maintained, but the bus cannot be used by other components during transfer, causing loss of time
Solution Approach 1:
The patent introduces a dedicated direct interface circuit as an intermediary between SRAM and non-volatile memory. This intermediary handles memory-to-memory transfers independently, allowing the main system bus to remain available for other components while still providing simple memory access operations through the interface circuit.
Data Source
AI summary
A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.