SRAM Cell N-Well Bias Control for Leakage and Failure Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SRAM cells face issues with write failures, read failures, and leakage current in standby mode due to constant bias on n-wells, which affect the performance and reliability of integrated circuits.
Innovation Solution
The SRAM cell array employs PMOS transistors as bit drivers and bit-bar drivers, and NMOS transistors as bit loads and bit-bar loads, with adjustable bias levels in n-wells during write, read, and transition to standby operations to optimize the performance and reduce failures and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If constant bias is applied to n-wells in SRAM cells, then the circuit structure is simple and easy to manufacture, but write failures and read failures occur and leakage current increases in standby mode
Solution Approach 1:
The patent applies dynamic biasing to the n-well, where the bias voltage is adjusted based on the operational mode (read, write, or standby) of the SRAM cell. During read operations, a first bias voltage is applied to enhance read margin; during write operations, a second bias voltage is applied to improve write ability; and during standby mode, a third bias voltage is applied to reduce leakage current. This dynamic adjustment resolves the contradiction by maintaining reliability across different operations while managing power consumption effectively.
Solution Approach 2:
The patent changes the bias voltage parameter of the n-well according to different operational requirements. By varying the bias voltage level (first bias voltage for read, second bias voltage for write, third bias voltage for standby), the patent optimizes the performance parameters such as read margin, write ability, and leakage current. This parameter change approach allows the circuit to achieve high reliability in each operational mode without compromising manufacturing simplicity.
2Ease of manufacture
If constant bias is applied to n-wells in SRAM cells, then the circuit structure is simple and easy to manufacture, but leakage current increases in standby mode
Solution Approach 1:
The patent implements dynamic biasing where the n-well bias voltage transitions from a constant level to a variable level that adapts to operational mode. In standby mode, a third bias voltage is specifically applied to minimize leakage current, while maintaining circuit structural simplicity. This dynamic approach reduces energy loss without complicating the manufacturing process.
Solution Approach 2:
The patent changes the bias voltage parameter of the n-well based on operational state. During standby mode, the bias voltage is adjusted to a third level that significantly reduces leakage current compared to constant biasing. This parameter adjustment effectively lowers energy loss while keeping the circuit structure simple and manufacturable.
3Reliability
If adjustable bias levels are applied to n-wells during different operations, then write failures and read failures are reduced and leakage current is minimized, but the circuit complexity increases
Solution Approach 1:
The patent employs dynamic biasing with three distinct bias voltage levels controlled according to operational mode. While this increases reliability by reducing write and read failures, the control mechanism is designed to manage complexity through systematic voltage switching. The bias control circuit responds to operational signals to apply the appropriate bias voltage, achieving high reliability with controlled complexity.
Solution Approach 2:
The patent utilizes parameter changes in the n-well bias voltage to optimize performance. By implementing three different bias voltage levels (first for read, second for write, third for standby), the patent significantly reduces write and read failures. The complexity introduced is managed through efficient voltage control logic that switches between bias levels based on operational requirements.
4Reliability
If adjustable bias levels are applied to n-wells during different operations, then leakage current is minimized in standby mode, but the circuit complexity increases
Solution Approach 1:
The patent implements dynamic biasing where the n-well bias voltage is adjusted based on operational mode. During standby mode, a third bias voltage is applied to minimize leakage current, while the control circuit manages complexity through systematic voltage switching. This dynamic approach achieves excellent leakage control with managed circuit complexity.
Solution Approach 2:
The patent changes the bias voltage parameter of the n-well according to operational state. In standby mode, the bias voltage is adjusted to a third level that significantly reduces leakage current. The complexity introduced is managed through efficient voltage control logic that switches between bias levels based on operational requirements, achieving low leakage with controlled complexity.
Data Source
AI summary
An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell.