SRAM One-Hot-of-Four Global Bit Line Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional SRAM designs consume excessive power due to the high capacitance and switching activity of global bit lines, which are typically active in both read and write cycles, leading to inefficiencies in power usage.
Innovation Solution
Implementing a one-hot-of-four configuration where only one global bit line is active at any point in a read or write cycle, utilizing paired local evaluators to communicate and manage signals across multiple global bit lines, thereby reducing power consumption by up to 50% compared to traditional designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional SRAM designs use multiple active global bit lines for read and write cycles, then data processing efficiency is maintained, but power consumption increases due to high capacitance and switching activity
Solution Approach 1:
The patent implements periodic action by using paired local evaluators that alternately activate different global bit lines. During read cycles, one evaluator activates while the other remains inactive, and vice versa for write cycles. This periodic activation pattern ensures that only one global bit line is active at any given time, reducing capacitance charging/discharging events while maintaining continuous data processing capability through the paired evaluator structure.
Solution Approach 2:
The patent applies segmentation by dividing the SRAM interface into paired local evaluators, each handling specific global bit lines. This segmentation allows independent control of different bit line groups, enabling selective activation of only the necessary evaluator and its associated global bit lines for each operation, thereby reducing overall power consumption while preserving data processing throughput.
2Use of energy by moving object
If only one global bit line is active at any point in read or write cycle, then power consumption is reduced by up to 50%, but device complexity increases due to paired local evaluators and signal coordination
Solution Approach 1:
The patent merges the functionality of multiple local evaluators into paired structures that share control logic and signal pathways. By combining evaluators into pairs that manage specific global bit line sets, the design reduces redundant circuitry while maintaining the one-hot-of-four configuration. This merging approach lowers device complexity compared to having fully independent evaluators for each global bit line.
Solution Approach 2:
The paired local evaluators are designed with multi-functionality, where each evaluator can handle both read and write operations on its assigned global bit lines. This universal design eliminates the need for separate dedicated evaluators for different operation types, reducing overall device complexity while enabling the power-efficient one-hot-of-four configuration.
Data Source
AI summary
A method in a computer-aided design system for generating a functional design model of a static random access memory is described herein. The method comprises generating a functional representation of a first local evaluation logic coupled to a first set of consecutive global bit lines (GBLs) and a first set of local bit lines (LBLs), the first local evaluation logic comprising a plurality of devices. The method further comprises generating a functional representation of a second local evaluation logic communicatively coupled to the first local evaluation logic via the devices; the second local evaluation logic is coupled to a second set of consecutive GBLs and a second set of LBLs. In addition, the second set of consecutive GBLs consecutive to the first set of consecutive GBLs, the first and second evaluation logics to generate signals from the LBLs such that one GBL is to be active at any point in a read or write cycle and the other GBLs are not concurrently active.