SRAM Output Circuit Pre-Charging to Reduce Bit Line Access Time
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Solution Overview
Problem
The access time of static random access memory (SRAM) is prolonged due to the presence of parasitic capacitors, which affects its performance, as the weak driving ability of SRAM cells leads to increased latency.
Innovation Solution
An output circuit is designed with a first pre-charge circuit to charge the read bit line to a logic high level, a sense amplifier to compare the voltage with the logic high state, and a latch circuit to generate comparison result signals, which helps in reducing access time by effectively managing the parasitic capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thousands of SRAM cells are coupled to a single output circuit, then memory capacity is increased, but parasitic capacitors are formed which increase latency and access time
Solution Approach 1:
The bit line is divided into multiple segmented bit lines (first bit line, second bit line, third bit line, fourth bit line) grouped into different bit line groups. Each segment is independently pre-charged and sensed, reducing the total parasitic capacitance burden on any single line and enabling parallel read operations that decrease access time while maintaining high memory capacity.
Solution Approach 2:
The patent implements pre-charge circuits that pre-charge the bit lines to a predetermined voltage level before the actual read operation. This preliminary action prepares the bit lines in advance, reducing the time required during the actual read cycle and compensating for the latency introduced by parasitic capacitors from multiple coupled SRAM cells.
2Use of energy by moving object
If SRAM cells have weak driving ability, then power consumption is reduced, but latency time increases due to parasitic capacitors
Solution Approach 1:
The patent combines multiple bit lines into bit line groups where the output signals from multiple SRAM cells are sensed simultaneously. This merging approach allows weak individual cell signals to be collectively amplified by shared sense amplifiers, reducing latency without requiring each cell to have strong driving ability, thus maintaining low power consumption.
Solution Approach 2:
Sense amplifiers are introduced as intermediary components between the SRAM cells and the output circuit. These amplifiers boost the weak signals from cells with weak driving ability, overcoming the latency caused by parasitic capacitors without increasing the power consumption of the cells themselves.
3Device complexity
If a conventional output circuit is used, then device complexity is low, but SRAM access time is prolonged and performance is reduced
Solution Approach 1:
The output circuit implements dynamic control through select circuits that can selectively connect different bit line groups to the sense amplifiers based on the read address. This dynamic switching capability allows the circuit to efficiently manage multiple bit lines and reduce access time by activating only the necessary read paths, improving SRAM performance without excessive complexity.
Solution Approach 2:
The sense amplifiers and pre-charge circuits serve multiple functions: they pre-charge bit lines, amplify weak signals from SRAM cells, and enable parallel read operations across multiple bit line groups. This multi-functionality improves SRAM performance and reduces access time without proportionally increasing device complexity.
Data Source
AI summary
An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, coupled to a read bit line which is coupled to a plurality of memory cells, pre-charging the voltage of the read bit line to a logic high level before a stored bit of a target memory cell is read to the read bit line, wherein the target memory cell is one of the plurality of memory cells, and a sense amplifier, coupled to the read bit line, detecting the voltage of the read bit line after the stored bit of the target memory cell is read to the read bit line, and comparing the voltage of the read bit line with the logic high level to respectively generate a comparison result signal and an inverse comparison result signal to a first output node and a second output node.