SRAM Device with Oxide Semiconductor Channels
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Solution Overview
Problem
Current SRAM devices face limitations in integration density, power consumption, and non-volatility, particularly due to the constraints of scaling and the volatility of conventional 6T SRAM, which cannot maintain information without power and has a relatively small degree of integration compared to other memory technologies.
Innovation Solution
The development of a static random-access memory (SRAM) device that incorporates a substrate with alternately stacked insulating and wiring layers, featuring transistors with silicon channels and oxide semiconductor channels, specifically using InMQ3(ZnO)m materials, to enhance integration, reduce power consumption, and increase non-volatility by vertically stacking PMOS and NMOS areas for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional 6T SRAM structure is used, then high operating speed is achieved, but integration density is limited due to six transistors per cell
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D vertical stacking architecture. Multiple transistor layers are stacked vertically above each other, allowing six transistors to be integrated in a compact footprint by utilizing the third dimension (vertical direction) rather than spreading them out horizontally. This dimensional transition directly reduces the layout area while maintaining the 6T SRAM functionality.
2Ease of manufacture
If conventional silicon channels are used in all transistors, then manufacturing simplicity is maintained, but power consumption is high due to leakage current
Solution Approach 1:
The patent applies different channel materials to different transistor types based on their functional requirements. PMOS transistors use conventional silicon channels for ease of manufacture and good hole mobility, while NMOS transistors use oxide semiconductor channels (such as IGZO) to achieve ultra-low leakage current. This localized material differentiation optimizes both manufacturing feasibility and power consumption by matching material properties to specific transistor roles.
3Speed
If conventional volatile memory architecture is used, then fast write access is achieved, but information is lost when power is cut off
Solution Approach 1:
The patent employs a hybrid memory architecture that combines volatile SRAM cells with non-volatile memory elements (such as phase change memory or resistive memory) in a composite structure. The SRAM portion provides fast write access for frequently accessed data, while the non-volatile portion retains information even when power is cut off. This composite material approach leverages the strengths of both volatile and non-volatile memory technologies to achieve both fast access and data retention.
Data Source
AI summary
Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.