Seven-Transistor SRAM Cell Using Parasitic Capacitance for Low-Voltage Writing
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Solution Overview
Problem
Conventional SRAM memory cells face challenges with increased cell size and reduced operation margin due to conflicting driving forces during readout and writing, especially at low voltages, leading to potential malfunction and instability.
Innovation Solution
A semiconductor storage device configuration using seven transistors, including PMOS and NMOS transistors, where the readout operation is driven by NMOS transistors without affecting the driving force ratio, and writing utilizes parasitic capacitance for data storage, allowing for stable low-voltage operation and reduced cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional 6-transistor SRAM cell is used, then the cell size is reduced, but the operation margin decreases and the cell becomes unstable during low-voltage operation due to conflicting driving forces during readout and writing
Solution Approach 1:
The patent divides the SRAM cell into two functional parts: a 6-transistor flip-flop for data storage and a separate write circuit using parasitic capacitance. This segmentation allows the readout operation to use only NMOS transistors without affecting the driving force ratio, while writing uses capacitance coupling through the parasitic capacitance of the NMOS transistor, resolving the conflict between readout and writing driving forces and improving operation margin
Solution Approach 2:
The patent introduces parasitic capacitance as an intermediary mechanism for writing data. Instead of relying on transistor driving forces for writing, the write operation uses capacitance coupling through the parasitic capacitance of the NMOS transistor, which acts as a mediator to transfer charge between bit lines and the storage node, eliminating the need to increase transistor size for writing
2Reliability
If transistor size is increased to improve writing capability, then the operation margin improves, but the cell size increases
Solution Approach 1:
The patent replaces the mechanical transistor-switching mechanism with a capacitance-based mechanism for writing operations. By using parasitic capacitance coupling instead of relying on transistor driving forces, the write operation can be performed without increasing transistor size, thus maintaining small cell size while improving operation margin through proper capacitance design
3Use of energy by moving object
If the driving force ratio is adjusted for low-voltage operation, then low-voltage operation becomes possible, but the cell becomes unstable and may malfunction
Solution Approach 1:
The patent makes the write mechanism dynamic by using time-dependent capacitance coupling. The write operation occurs during a specific time window when the parasitic capacitance is actively coupled between bit lines and storage nodes, allowing low-voltage operation during this dynamic period without compromising stability during static storage phases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables stable operation with improved margin characteristics and reduced cell size, preventing instability and malfunction during low-voltage operations by eliminating driving force ratio issues and leveraging capacitance coupling for writing.
Implementation Method 1
writing utilizes parasitic capacitance for data storage, allowing for stable low-voltage operation and reduced cell size
Data Source
AI summary
According to one embodiment, a first node is connected to a gate of a second PMOS and a gate of a second NMOS, a second node is connected to a gate of a first PMOS and a gate of a first NMOS, a gate of the first transistor is connected to a first signal line, a source of a first transistor is connected to the first node, and a drain of the first transistor is connected to the second node, a gate of a second transistor is connected to the second node, a source of the second transistor is connected to a third node, and a drain of the second transistor is connected to a second signal line, and a gate of a third transistor is connected to a third signal line, a source of the third transistor is connected to a fourth signal line, and a drain of the third transistor is connected to the third node.