SRAM Pass Transistor Defect Screening via Dynamic Stress
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Solution Overview
Problem
Conventional manufacturing tests for SRAMs are ineffective in identifying memory cells vulnerable to early life write failures due to bit line side pass transistor defects, which can pass initial screening but fail later due to increased variability and channel hot carrier conduction, leading to write failures.
Innovation Solution
A dynamic stress method is applied during manufacturing, involving repeated writing and reading of alternating data states under elevated voltage conditions to accelerate defects, followed by a write screen test with forward back-bias to identify and replace vulnerable cells, thereby enabling the use of redundancy techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing tests are used for SRAMs, then production efficiency is maintained, but memory cells vulnerable to early life write failures due to bit line side pass transistor defects cannot be identified
Solution Approach 1:
The patent applies dynamic stress with alternating data states before the final write screen test to accelerate defects in pass transistors. This preliminary action causes latent defects to manifest as write failures, enabling their identification before product shipment. The stress phase is performed in advance to reveal vulnerabilities that would otherwise remain hidden during conventional testing.
Solution Approach 2:
The patent changes the test parameters by applying elevated voltage conditions and dynamic stress with alternating data states (0 and 1) during the stress phase. These parameter changes accelerate the manifestation of defects in bit line side pass transistors, making vulnerable cells fail the subsequent write screen test. This allows differentiation between good cells and those prone to early life failures.
2Reliability
If dynamic stress method is applied to identify vulnerable cells, then reliability improves by reducing early life write failures, but manufacturing time and process complexity increase
Solution Approach 1:
The patent employs periodic action by repeatedly writing alternating data states (0 and 1) to memory cells during the dynamic stress phase. This periodic switching accelerates defect manifestation in pass transistors through hot carrier injection and other degradation mechanisms. The repeated cycling of data states exposes vulnerable cells that would fail under stress but pass under normal conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach efficiently distinguishes vulnerable cells from good ones without yield loss, effectively reducing early life write failures by identifying and replacing defective cells before they cause operational issues.
Implementation Method 1
bit line side pass transistor defects, which can pass initial screening but fail later due to increased variability and channel hot carrier conduction
Data Source
AI summary
A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.