SRAM Peripheral Circuitry Voltage Segmentation
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Solution Overview
Problem
Existing SRAM memory designs face challenges in reducing power consumption, particularly in embedded SRAMs within integrated circuits, due to high minimum supply voltage requirements, which lead to increased power consumption during standby cycles and limited area efficiency in peripheral circuitry.
Innovation Solution
A circuit and method that provide a reduced voltage to peripheral circuitry while maintaining a higher supply voltage to the SRAM cell array using a level shifter circuit, allowing for efficient power management across different operational modes, such as active, standby, and sleep modes, without adding significant area penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high minimum supply voltage is maintained to ensure proper data storage and retrieval in scaled CMOS processes, then data retention and noise margins are improved, but power consumption increases significantly during standby cycles
Solution Approach 1:
The patent segments the SRAM block into two distinct voltage domains: the cell array operates at a higher voltage (Vcc1) to ensure reliable data storage and retrieval, while the peripheral circuitry operates at a lower voltage (Vcc2) to reduce power consumption. This segmentation allows each part to operate at its optimal voltage level, resolving the contradiction between reliability and energy efficiency.
Solution Approach 2:
Different voltage levels are applied to different parts of the SRAM block based on their specific functional requirements. The cell array receives a higher voltage to maintain data integrity and noise margins, while the peripheral circuitry receives a lower voltage to minimize power consumption during standby. This local quality approach ensures that voltage is optimized for each specific component's needs.
2Use of energy by moving object
If the supply voltage to the SRAM block is reduced to lower power consumption, then energy efficiency is improved, but the minimum supply voltage requirement for correct data storage and retrieval is not met
Solution Approach 1:
The patent divides the SRAM block into cell array and peripheral circuitry, allowing the cell array to operate at a higher voltage (Vcc1) sufficient for reliable data storage and retrieval, while the peripheral circuitry operates at a lower voltage (Vcc2) to reduce power consumption. This segmentation enables the system to meet minimum voltage requirements for data integrity while minimizing overall power consumption.
Solution Approach 2:
The patent implements dynamic voltage adjustment capability through voltage regulators that can independently control the voltage supplied to the cell array and peripheral circuitry. This allows the system to adapt voltage levels based on operational mode (active or standby), ensuring reliable data storage when needed while reducing power consumption during idle periods.
3Area of stationary object
If peripheral circuitry is integrated adjacent to the SRAM cell array to improve area efficiency, then device density is improved, but power consumption increases due to the additional circuitry operating at high voltage
Solution Approach 1:
The patent segments the voltage supply to different parts of the integrated SRAM block, allowing the peripheral circuitry integrated adjacent to the cell array to operate at a lower voltage (Vcc2) than the cell array (Vcc1). This maintains the area efficiency benefits of integration while reducing the power consumption of the peripheral circuitry through localized voltage reduction.
Solution Approach 2:
The patent applies different voltage levels to different spatial regions of the SRAM block: the cell array region operates at a higher voltage to ensure reliable data storage, while the peripheral circuitry region operates at a lower voltage to minimize power consumption. This local quality approach optimizes both area efficiency and power consumption by tailoring voltage to each region's functional requirements.
Data Source
AI summary
A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circuitry for the SRAM memory. A level shifter circuit is provided coupled to the lower power supply and outputting a higher supply voltage. An array of SRAM memory cells that may comprise 4T, 6T or 8T static RAM memory cells are coupled to the higher supply voltage during read and write operations. Operating the peripheral circuitry of the SRAM memory at the lower supply voltage achieves reduced power consumption for the SRAM memory and the integrated circuit.