2-Port SRAM Layout with Perpendicular Word Lines
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Solution Overview
Problem
Existing layout structures for 2-port SRAM memory cells are not suitable for read/write operations in two directions perpendicular to each other, leading to increased area requirements due to the need for separate wiring directions and adjacent memory cell separation.
Innovation Solution
A layout structure for 2-port SRAM memory cells with first and second word lines extending in perpendicular directions, featuring gate interconnects that extend in one direction and are arranged in three rows perpendicular to it, allowing for secure sizing and connection of memory cells with vias for reduced area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the layout structure from Patent Document 2 is applied to 2-port SRAM with perpendicular read/write directions, then the wiring directions must be changed or adjacent memory cells must be separated, but this increases the area of the memory cell array
Solution Approach 1:
The patent applies asymmetry by configuring the gate interconnects in an asymmetric three-row arrangement rather than a symmetric layout. The first, second, and third rows are positioned at different vertical locations to accommodate the perpendicular word lines and bit line pairs, allowing the memory cell to support read/write operations in two perpendicular directions without increasing area.
Solution Approach 2:
The patent utilizes the vertical dimension by arranging gate interconnects in three rows extending in the first direction (horizontal) while positioned at different vertical locations. This three-dimensional arrangement of interconnects allows perpendicular wiring directions to coexist within the same planar footprint, enabling adaptability to multi-directional access without area expansion.
2Length of stationary object
If gate interconnects are arranged in three rows extending in the first direction, then the size of the memory cell in the second direction can be sufficiently secured, but the layout complexity increases
Solution Approach 1:
The gate interconnects are segmented into three distinct rows (first, second, and third rows) that extend in the first direction. This segmentation allows each row to be independently positioned vertically, facilitating proper spacing and connection for perpendicular word lines and bit line pairs while maintaining sufficient memory cell size in the second direction.
Solution Approach 2:
The three rows of gate interconnects serve multiple functions simultaneously: they provide electrical connections for p-type and n-type transistors, accommodate perpendicular wiring directions, and define the vertical boundaries of the memory cell. This multi-functionality reduces layout complexity despite the increased arrangement sophistication.
Data Source
AI summary
A memory cell of a 2-port static random access memory (SRAM) includes first and second p-type transistors and first to sixth n-type transistors. Gate interconnects extend in the X direction and are arranged in three rows in the Y direction. The gate interconnects in the first row form gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor, the gate interconnect in the second row forms gates of the fifth and sixth n-type transistors, and the gate interconnects in the third row form gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.