SRAM Pillar SGT Layout for High Density Integration
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high integration and performance for SRAM circuits using Surrounding Gate Transistors (SGTs), particularly in reducing chip size and increasing density while maintaining effective transistor functionality.
Innovation Solution
A manufacturing method for forming SRAM circuits with SGTs involves a precise arrangement and patterning process using multiple mask layers and etching techniques to create aligned semiconductor pillars and gate conductor layers, allowing for high-density integration by optimizing the layout and connection of SGTs within the SRAM cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar MOS transistor structures are used, then manufacturing process is simple, but device density and integration level are low
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional pillar-shaped SGT structures. The channel extends vertically from the substrate surface, utilizing the third dimension (depth) to increase device density. Multiple pillars can be arranged in a compact footprint, achieving higher integration levels while maintaining manufacturability through established semiconductor fabrication processes.
2Area of stationary object
If chip size is reduced for higher integration, then area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The SRAM cell is segmented into distinct functional regions with clearly defined pillar arrangements. Selective pillars are positioned at corners, driving pillars at center positions, and loading pillars at intermediate positions. This segmentation creates a modular structure that simplifies alignment requirements and enables precise manufacturing through standardized fabrication steps.
Solution Approach 2:
The patent establishes predetermined pillar positions and arrangements before fabrication begins. The pillar locations are pre-planned based on circuit functionality requirements, allowing manufacturing processes to follow established patterns rather than requiring complex real-time adjustments, thereby maintaining precision while reducing chip area.
3Productivity
If more SGTs are integrated per SRAM cell, then circuit performance improves, but device complexity increases
Solution Approach 1:
The patent employs multiple pillars within each SRAM cell that can serve different functions (selective, driving, loading) based on their positions and connections. This multi-functional arrangement allows the circuit to achieve high performance with six or eight pillars per cell while maintaining a systematic and manageable structure. The same basic pillar configuration can be replicated across multiple cells, reducing overall complexity.
Data Source
AI summary
In a SRAM cell, a Si pillar, which is a selection SGT in upper row of Si pillars, is located on the left end in X direction. A Si pillar, which is a selection SGT in lower row of Si pillars, is located on the right end. The Si pillar of the lower row is present in a width of an area extended from a contact hole in Y direction in planar view. Then, the Si pillar of the upper row is present in a width of an area extended from a contact hole in Y direction in planar view. In each of the upper row and the lower row, a TiN layer, which is a gate electrode for a loading SGT and a driving SGT, is formed to contact at side surface of entire gate region in a vertical direction between the corresponding Si pillars.