SRAM Read Circuit PMOS Leakage Suppression
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Solution Overview
Problem
Conventional SRAMs experience significant electric leakage, leading to increased power consumption and data read errors due to leakage currents, which limit the number of storage units that can be mounted on a read bit line and affect storage density.
Innovation Solution
Incorporating at least one PMOS transistor in the electric leakage path of the read circuit to suppress leakage currents, allowing the read bit line to maintain a correct level even when other storage units have leakage, thereby preventing data read errors and enabling more storage units to be mounted, thus improving storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional SRAM structure with NMOS transistors is used, then the circuit can be manufactured with standard processes, but the leakage current increases significantly leading to high power consumption
Solution Approach 1:
The patent changes the transistor type parameter from NMOS to PMOS in the read circuit to exploit the lower leakage current characteristic of PMOS devices, directly reducing power consumption while maintaining circuit functionality
Solution Approach 2:
The patent introduces a PMOS transistor as an intermediary component in the read circuit's leakage path to suppress leakage current without fundamentally redesigning the entire SRAM structure, achieving power reduction with minimal complexity increase
2Quantity of substance
If more storage units are mounted on the read bit line, then storage density increases, but the leakage current from multiple storage units accumulates causing data read errors
Solution Approach 1:
The patent converts the harmful leakage current into a beneficial suppression mechanism by using PMOS transistors whose natural lower leakage characteristic actively counteracts the cumulative leakage from multiple storage units, enabling higher storage density without sacrificing read accuracy
3Speed
If NMOS transistors are used in the read circuit, then the transistor has higher electron mobility and faster switching, but the leakage current path causes static power consumption
Solution Approach 1:
The patent applies different transistor types in different locations: PMOS transistors are specifically placed in the read circuit's leakage path where leakage suppression is critical, while other parts of the circuit can use NMOS transistors for high-speed performance, achieving local optimization of both speed and power
Data Source
AI summary
A storage array includes a read bit line, a ground, a read bit line switch of the read bit line, and a plurality of storage circuits. Each storage circuit includes a storage unit configured to store data and a read circuit configured to read data from the storage unit. A data input end of the read circuit is connected to a data output end of the storage unit, to read data from the storage circuit, and a data output end of the read circuit is connected to the read bit line, to output the read data to the read bit line. There is at least one PMOS transistor in an electric leakage path from a power supply to the read bit line in the read circuit, to suppress a leakage current in the read circuit.