Power Gate for SRAM Latch-Up Prevention
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Solution Overview
Problem
In CMOS circuits, particularly during SRAM cell testing or normal operating voltages, the P/N junction between the source of a PFET and the Nwell can become forward-biased, leading to potential latch-up issues when the Nwell voltage differs from the power supply voltage VDD.
Innovation Solution
Charging the positive voltage node and Nwell regions of an SRAM array at approximately the same rate to maintain the P/N junction in a reverse-biased state, using specific timing of signals S1 and E1 to ensure synchronized voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the Nwell voltage is set different from VDD during testing or operation, then testing flexibility and operational versatility are improved, but the P/N junction between the source of PFET and the Nwell becomes forward-biased causing latch-up
Solution Approach 1:
The patent applies preliminary action by raising the Nwell voltage to match VDD before applying or raising the positive voltage at the source of the PFET. This sequence prevents the P/N junction from becoming forward-biased during voltage transitions, thereby preventing latch-up while allowing the Nwell to operate at different voltages during normal operation and testing.
2Reliability
If the source of PFET and Nwell are both connected to VDD, then latch-up is prevented, but testing flexibility is reduced due to voltage constraints
Solution Approach 1:
The patent implements dynamics by making the Nwell voltage controllable and adjustable rather than fixed at VDD. The Nwell voltage can be dynamically changed to match VDD when needed for latch-up prevention, and can operate at different voltages during normal operation and testing, providing both reliability and flexibility.
3Device complexity
If the positive voltage node is charged before the Nwell, then power-up sequence is simplified, but the P/N junction becomes forward-biased causing latch-up
Solution Approach 1:
The patent uses feedback through control logic that monitors the voltage states of the positive voltage node and Nwell, and adjusts the charging sequences accordingly. This feedback mechanism ensures that the Nwell voltage is raised to match VDD before the positive voltage node is charged, preventing latch-up while maintaining a systematic power-up procedure.
Data Source
AI summary
In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.