SRAM Power Line Selection Circuitry for Leakage Reduction
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Solution Overview
Problem
Existing SRAM architectures face challenges in balancing write and read operations while controlling dynamic leakage, often requiring separate circuit solutions that increase device area and utilize additional voltage supplies.
Innovation Solution
A system and method that integrate dynamic leakage reduction with a write-assisted SRAM architecture by using power line selection circuitry to locally convert voltages for both read and write operations, reducing the area overhead and eliminating the need for external voltage supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuit solutions are used for write assistance and leakage control, then write performance and leakage reduction are improved, but device area increases
Solution Approach 1:
The patent combines write assistance and leakage control functions into a single integrated circuit solution. The power line selection circuitry merges the write assist transistor and leakage control transistor into one structure, eliminating the need for separate circuits and reducing overall device area while maintaining both write performance and leakage reduction benefits.
Solution Approach 2:
The integrated power line selection circuitry performs multiple functions simultaneously: it provides write assistance by lowering voltage during write operations and controls leakage by adjusting power line voltage during idle periods. This multi-functional design eliminates the need for dedicated separate circuits for each function.
2Loss of energy
If separate circuit solutions are used for write assistance and leakage control, then dynamic leakage reduction is improved, but device area increases
Solution Approach 1:
The patent merges leakage control and write assistance circuits into a single power line selection circuitry, reducing device area while maintaining effective leakage reduction. The integrated design allows the same circuit structure to serve both leakage control and write assist functions without requiring additional separate components.
Solution Approach 2:
The patent uses parameter changes (voltage level adjustments) to control leakage dynamically. By changing the power line voltage from VDD to a lower level (VDD - Vth) during idle periods, the circuit achieves leakage reduction without requiring additional hardware, thereby avoiding area increase.
3Reliability
If additional voltage supplies are used for write operations, then write assistance is improved, but device complexity increases
Solution Approach 1:
The write assist transistor is configured to automatically reduce the voltage on the power line during write operations without requiring external voltage supplies. The transistor activates based on the write signal, self-managing the voltage reduction function and simplifying the overall device architecture by eliminating external voltage supply requirements.
Solution Approach 2:
The power line selection circuitry acts as an intermediary between the write signal and the SRAM cells, mediating the voltage transformation. Instead of requiring external voltage supplies, the circuit uses the write signal to control the power line selection transistor, which then provides the necessary voltage adjustment directly at the cell level.
4Productivity
If access transistor on-resistance is reduced for write operations, then write performance is improved, but cell stability during read operations deteriorates
Solution Approach 1:
The patent applies dynamic voltage control to the power line, adjusting the voltage level based on the operation type (read or write). During write operations, the voltage is reduced to assist writing; during read operations, the voltage returns to normal levels to maintain cell stability. This dynamic adjustment allows the system to optimize for the current operation without permanently compromising cell stability.
Solution Approach 2:
The patent changes the power line voltage parameter dynamically based on operation mode. By switching between VDD (for read/stability) and VDD - Vth (for write assistance), the system achieves both good write performance and cell stability without requiring permanently reduced on-resistance that would compromise stability.
Data Source
AI summary
A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.