SRAM Switchable Power Paths for IR Drop Mitigation
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Solution Overview
Problem
As memory devices, such as SRAM, are scaled down, the oxide diffusion area becomes smaller, leading to increased resistance in backside power vias and a larger voltage drop (IR drop), which degrades the speed and performance of the SRAM.
Innovation Solution
The introduction of a footer/header system that allows for switchable power delivery paths, enabling the SRAM to switch between single-side and double-side power rails. This system minimizes leakage during standby/retention mode and facilitates high-speed operation during mission mode by optimizing power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory devices are scaled down in size, then device dimensions are reduced, but resistance in backside power vias increases and voltage drop increases
Solution Approach 1:
The power delivery system is segmented into multiple independent power delivery paths, including first and second power delivery paths from the backside and third and fourth power delivery paths from the frontside. This segmentation allows current to be distributed across multiple routes, reducing the resistance and voltage drop in each individual path while maintaining effective power delivery to the memory cell despite device scaling.
2Area of moving object
If oxide diffusion area is reduced, then device size is reduced, but resistance in power vias increases
Solution Approach 1:
The invention transitions from relying solely on backside power delivery to utilizing both backside and frontside power delivery paths. By adding power delivery routes from the frontside (third and fourth power delivery paths), the system effectively adds another dimension to the power distribution architecture, compensating for the increased resistance caused by reduced oxide diffusion area and via size.
3Productivity
If voltage drop increases, then power delivery efficiency decreases, but device scaling continues
Solution Approach 1:
The invention merges multiple power delivery paths (first, second, third, and fourth paths) into a unified power delivery system. By combining these parallel paths, the total current can be distributed across all routes, reducing the overall voltage drop and power loss while enabling continued device scaling. The merged system provides redundant and complementary power delivery routes that compensate for losses in individual paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates the IR drop issue, improving the speed and performance of SRAM during mission mode while conserving power during standby/retention mode, thus enhancing overall power management and efficiency.
Implementation Method 1
a first conductor structure disposed on a backside of the substrate and configured to carry a supply voltage
Data Source
AI summary
A memory device may comprise a substrate, a plurality of memory cells, and a header device. The substrate may have a first side and a second side opposite to each other. The plurality of memory cells may be formed on the first side of the substrate. The header device may be formed on the first side of the substrate. The header device can be configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.