SRAM Cell Power Selection Logic for RC Time Constant Mitigation
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Solution Overview
Problem
In integrated circuits, memory cells far from data or address drivers face slow write/read speeds due to large RC time constants in long data lines, which cannot be sufficiently mitigated by increasing voltage at pass gates, and adding buffers complicates the circuitry and is difficult to test for proper operation.
Innovation Solution
Incorporating power selection logic in memory cells to disconnect storage inverters from the reference voltage source during write operations, allowing data to be driven on the data lines and flipping the state of the inverters without internal voltage contention, thus reducing the impact of large RC time constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If buffers are added along data lines to overcome RC time constants, then write/read speeds are improved, but circuit complexity and area increase
Solution Approach 1:
The patent extracts the problematic RC time constant effect by selectively disconnecting the storage inverters from the power supply during write operations. This removes the internal voltage drive that conflicts with data line voltage transitions, effectively eliminating the need for buffers while maintaining fast write speeds.
Solution Approach 2:
The patent introduces dynamic power supply control where the storage inverters are selectively connected and disconnected from the power supply based on the operation mode (read vs. write). During writes, the inverters are disconnected to avoid contention; during reads, they are connected to maintain stored values. This dynamic adjustment optimizes performance without adding buffers.
2Speed
If voltage on address lines is increased to counter RC time constants, then pass gate performance is improved, but data line RC effects remain detrimental
Solution Approach 1:
The patent converts the harmful effect of the storage inverters' internal voltage drive into a beneficial disconnection mechanism. By intentionally disconnecting the inverters during writes, the data line voltage transitions are no longer opposed by internal currents, allowing fast write operations without needing to increase address line voltages.
3Stability of the object's composition
If storage inverters remain connected to power supply during write operations, then internal state is maintained, but voltage contention slows down write speed
Solution Approach 1:
The patent implements periodic connection and disconnection of the power supply to the storage inverters based on the operation phase. During write operations, the inverters are disconnected from power to eliminate voltage contention and enable fast writes. During read operations and idle states, the inverters are connected to maintain their stored state. This periodic control achieves both fast writes and state stability.
Data Source
AI summary
Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.