SRAM Power Switch Circuit for Low Voltage Writeability
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Solution Overview
Problem
Existing SRAM cell designs face challenges in maintaining stability and writeability, especially at low operating voltages, due to issues with access transistor threshold voltage increases and read disturbance, which affects their performance in both low voltage and temperature variations.
Innovation Solution
The implementation of a power switch circuit that selectively connects a power source with cross-coupled logic gates in SRAM cells, allowing for improved writeability and stability by interrupting power supply during write operations and maintaining power during read operations, using bidirectional read/write ports and single or differential read ports to facilitate low voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the size of NMOS access transistors is increased to improve writeability, then writeability is improved, but read disturbance increases and static noise margin decreases
Solution Approach 1:
The power supply to the cross-coupled logic gates is segmented through switch circuits that can independently control power delivery to each gate. This allows selective powering of gates during different operations (write vs. read), resolving the contradiction by enabling large access transistor sizes for writeability while preventing read disturbance through controlled power interruption during read operations
Solution Approach 2:
The patent implements dynamic power control where the power supply connection to cross-coupled logic gates is changed based on operational mode. During write operations, power is maintained to both gates; during read operations, power is selectively interrupted to prevent read disturbance. This dynamic adaptation allows the system to optimize performance for each operation type without compromising the other
2Use of energy by moving object
If operating voltage is reduced to lower power consumption, then power consumption decreases, but writeability deteriorates due to access transistor threshold voltage issues
Solution Approach 1:
The patent applies preliminary anti-action by preemptively interrupting power to specific cross-coupled logic gates during write operations when needed. This prevents the threshold voltage issue from manifesting by controlling the power state of access transistors before write operations occur, allowing low voltage operation while maintaining writeability through selective power management
Solution Approach 2:
The patent changes the power supply parameter dynamically based on operational requirements. By switching the power state of cross-coupled logic gates between different operational modes (write vs. read), the system can operate at lower voltages while maintaining adequate writeability when power is appropriately controlled, thus resolving the contradiction between low power consumption and writeability
3Stability of the object's composition
If power is continuously supplied to cross-coupled logic gates to maintain stability, then stability is improved, but read disturbance increases
Solution Approach 1:
The patent implements periodic power supply control where power to cross-coupled logic gates is selectively interrupted during read operations and restored for write operations. This periodic on/off cycling of power supply prevents read disturbance by removing power during reads while maintaining stability during writes, resolving the contradiction between continuous stability and read disturbance prevention
Data Source
AI summary
Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions.