SRAM Precharge Circuit for Opening Failure Detection
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Solution Overview
Problem
In two-port SRAMs, detecting bit line states and opening failures is challenging due to bias issues in the sense amplifier, leading to difficulties in identifying defective products during manufacturing.
Innovation Solution
A semiconductor storage device with a precharge circuit that sets read bit lines to different potentials and a sense amplifier circuit that amplifies potential differences, allowing for the detection of opening failures by adjusting precharge levels and delaying the sense amplifier enable signal to ensure accurate reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard sense amplifier is used in two-port SRAM, then the reading operation can be performed, but opening failures cannot be reliably detected due to sense amplifier bias
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to different potentials before the reading operation. Specifically, the first bit line is precharged to a first potential and the second bit line is precharged to a second potential that is lower than the first potential. This preliminary differentiation of bit line potentials enables the sense amplifier to reliably detect opening failures by comparing the potential difference, overcoming the bias issue that would otherwise prevent accurate detection.
2Ease of operation
If both bit lines are precharged to the same high level, then normal reading can occur, but opening failures remain undetectable due to sense amplifier bias
Solution Approach 1:
The patent applies asymmetry by intentionally creating an asymmetric precharge state where the first bit line is charged to a higher potential than the second bit line. This asymmetric potential distribution breaks the symmetry that causes sense amplifier bias, enabling the amplifier to correctly identify opening failures. The asymmetric precharge levels create a reference condition that allows reliable detection when an opening failure occurs.
3Speed
If the sense amplifier is enabled immediately, then reading speed is maintained, but opening failures cannot be distinguished from normal operations
Solution Approach 1:
The patent performs preliminary action by precharging bit lines to different potentials before enabling the sense amplifier. This preliminary setup creates a baseline condition where any potential difference detected during reading can be reliably attributed to an opening failure rather than being masked by sense amplifier bias. The delayed enablement of the sense amplifier after asymmetric precharging ensures both speed and accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable detection of opening failures and ensures high-quality multiple-port SRAMs by accurately distinguishing between normal and defective products, enhancing manufacturing reliability.
Implementation Method 1
a precharge circuit (24) configured to charge, before reading from the memory cell, the first read bit line to a first potential and the second read bit line to a second potential lower than the first potential
Implementation Method 2
a sense amplifier circuit (28) configured to amplify a difference in potential between the first read bit line and the second read bit line during the reading from the memory cell
Data Source
AI summary
A semiconductor storage device comprises a memory cell, a write word line and a read word line connected to the memory cell, first and second write bit lines connected to the memory cell, first and second read bit lines connected to the memory cell, a precharge circuit, and a sense amplifier circuit. The precharge circuit is configured to charge, before reading from the memory cell, the first read bit line to a first potential and the second read bit line to a second potential lower than the first potential. The sense amplifier circuit is configured to amplify a difference in potential between the first read bit line and the second read bit line during the reading from the memory cell and output a signal corresponding to the difference in potential as a read value.