SRAM Precharge Voltage Adjustment for Static Noise Margin
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Solution Overview
Problem
Current SRAM memory devices face challenges in maintaining optimal reading and writing margins due to electrical variability caused by smaller component sizes and lower supply voltages, leading to perturbations during memory cell reading operations.
Innovation Solution
A memory device with a modified SRAM structure that generates a precharge voltage lower than the nominal supply voltage, using a matrix of modified memory cells with adjustable ratios of nMos and pMos transistors to optimize the Static Noise Margin (SNM) for improved reading performance without compromising security margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the precharge voltage of bit lines is set to the nominal supply voltage Vdd, then the reading operation can be performed, but the Static Noise Margin (SNM) is degraded due to electrical variability from smaller component sizes
Solution Approach 1:
The patent changes the precharge voltage parameter from the nominal supply voltage Vdd to a reduced voltage level. This parameter change directly addresses the SNM degradation caused by smaller component sizes and lower supply voltages, improving reading reliability without requiring changes to the physical component structure
Solution Approach 2:
The patent applies preliminary action by precharging the bit lines to a reduced voltage level before the actual reading operation. This preliminary voltage adjustment creates more favorable conditions for the subsequent reading operation, ensuring that the memory cell can be read reliably even with degraded margins from scaling
2Reliability
If the precharge voltage is reduced to improve reading margin, then the SNM is enhanced, but the operating range for voltage adjustment is constrained
Solution Approach 1:
The patent introduces dynamic voltage adjustment capability through a voltage control signal that can modulate the precharge voltage level. This dynamic approach allows the system to adapt the precharge voltage within an optimized range, balancing reading margin improvement with operational flexibility
Data Source
AI summary
A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.