SRAM Bit Cell PUF Generator for Real-Time Authentication
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Solution Overview
Problem
Current SRAM-based PUF generators face limitations such as restricted access during boot time and inadequate CRP space, failing to provide strong PUF configurations and real-time query capabilities while maintaining low power consumption and high throughput.
Innovation Solution
A PUF generator design that incorporates a PUF cell array with bit cells arranged in a column-row configuration, utilizing stressed read/write techniques to determine intrinsic tendencies of bit cells, allowing for stable logical states to generate unique PUF signatures, enabling real-time access and large CRP space without requiring additional hardware or power cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SRAM-based PUF generator is used, then unique PUF signature can be generated based on manufacturing variations, but access is restricted to boot time only and CRP space is limited
Solution Approach 1:
The patent enables dynamic access to PUF generators during runtime by implementing a memory-based PUF structure that can be selectively accessed through control logic, transitioning from static boot-time-only access to flexible runtime access while maintaining PUF signature reliability
Solution Approach 2:
The PUF generator is divided into multiple independently accessible memory blocks or regions, allowing selective access to different PUF instances during runtime, thereby increasing adaptability without compromising the cryptographic strength of individual PUF configurations
2Adaptability or versatility
If SRAM-based PUF generator is used, then PUF signature can be generated, but power consumption increases when additional hardware is added to enable runtime access
Solution Approach 1:
The patent implements a multi-functional memory structure that serves both as standard memory and as PUF generator, allowing the same hardware to perform multiple functions without requiring additional dedicated PUF hardware, thereby avoiding extra power consumption
Solution Approach 2:
The memory-based PUF structure utilizes the inherent physical properties of the memory cells themselves to generate PUF signatures, eliminating the need for separate PUF hardware circuits and reducing overall power consumption while enabling runtime access
3Reliability
If conventional authentication approaches are used, then device identity can be inscribed, but the identity can be easily mimicked and reverse engineered
Solution Approach 1:
The patent uses the physical manufacturing variations of memory cells as an unclonable template for authentication, where the unique PUF signature is derived from inherent physical differences that cannot be copied or reverse-engineered, providing security without additional complex hardware
Data Source
AI summary
Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two pre-charge transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-charged with substantially the same voltages by the respective at least two pre-charge transistors allowing each of the plurality of bit cells having a first metastable logical state; and an authentication circuit, coupled to the PUF cell array, wherein the authentication circuit is configured to access and determine second logical states of bit cells in at least one row of the PUF cell array by turning on the at least one enable transistor and turning off the at least two pre-charge transistors of each of the bit cell in the at least one row of the PUF cell array, and based on the determined second logical states of the bit cell in the at least one row of the PUF cell array, to generate a PUF signature.