Dual-Mode SRAM PUF Circuit for Reliable Low-Overhead Entropy
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Solution Overview
Problem
Existing SRAM PUF circuits in IoT equipment face reliability issues due to environmental disturbances affecting power-on states, while monostable PUF circuits with separate arrays incur high hardware overheads.
Innovation Solution
A sub-threshold monostable PUF circuit with an SRAM function and entropy source extraction, incorporating a mode configuration circuit, decoding circuit, and reading circuit, which allows the SRAM array to operate in both SRAM storage and PUF modes, utilizing pre-charge modules and transistors to generate entropy source voltages with low overheads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SRAM PUF circuit uses bistable cross-coupled inverters for entropy source generation, then hardware overhead is reduced by reusing existing SRAM array, but reliability deteriorates due to environmental disturbance affecting power-on states
Solution Approach 1:
The circuit dynamically transitions between bistable and monostable modes by controlling the third mode configuration ports. In PUF mode, the circuit operates as monostable with equalized bit line voltages through pre-charge modules, eliminating environmental sensitivity. In SRAM mode, it operates as bistable for normal storage. This dynamic reconfiguration resolves the contradiction by enabling reliable PUF operation without permanent structural changes.
Solution Approach 2:
The invention changes the operating parameters of the SRAM cell by applying specific voltage levels to the third mode configuration ports. When these ports receive high level signals, the cross-coupled inverters operate in monostable region with process deviation-determined equilibrium, rather than bistable region. This parameter change enables the same hardware to achieve both low overhead and high reliability.
2Reliability
If monostable PUF circuit uses separate PUF array design, then reliability improves by determining entropy source voltage through process deviation, but hardware overhead increases due to additional array design
Solution Approach 1:
The SRAM cell is designed to perform multiple functions: normal data storage in SRAM mode and entropy source generation in PUF mode. By adding mode configuration ports and pre-charge modules, the same cell structure can be universally used for both purposes, eliminating the need for separate PUF arrays and reducing hardware overhead while maintaining reliability.
Solution Approach 2:
The invention merges the PUF array functionality with the existing SRAM array by integrating mode configuration circuits and pre-charge modules into the SRAM cell structure. This combination allows the SRAM array to serve dual purposes, reducing overall hardware overhead while achieving reliable PUF operation through process deviation exploitation.
Data Source
AI summary
A sub-threshold monostable PUF circuit with an SRAM function and an entropy source extraction function includes a mode configuration circuit, a decoding circuit, a PUF array and a reading circuit. The PUF array has a SRAM storage mode and a PUF mode for generating an entropy source voltage. The PUF array includes m*n PUF cells and n pre-charge modules. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor. The monostable PUF array formed by PUF cells is constructed only by adding a first PMOS transistor, a first NMOS transistor and a fourth NMOS transistor in each SRAM cell of an original SRAM storage array of IoT equipment.