SRAM PUF Latch Precharge Through Bit Lines for Lower Error Rates
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Solution Overview
Problem
SRAM PUF bit cells exhibit high natural error rates due to voltage, temperature, and aging changes, leading to limited reduction in error rates with existing error reduction methods, which are also resource-intensive and costly.
Innovation Solution
A PUF bit cell design incorporating a latch, transmission gates, and a digital-to-analog converter (DAC) for precharging and regenerating the latch, allowing for the assessment and selection of bit cells with large natural offsets to reduce error rates, thereby improving bit error rate (BER).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If SRAM PUF bit cells are used, then area is reduced compared to other PUF approaches, but error rates increase to as high as 15 percent due to voltage, temperature, and aging changes
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to a specific voltage level before reading the PUF bit cell. This precharge action prepares the circuit in advance to compensate for voltage, temperature, and aging variations, thereby reducing error rates without increasing area. The precharge voltage is set to counteract the drift in trip point caused by environmental changes.
2Reliability
If repeated reads are performed to determine bit reliability, then error reduction is achieved, but area, time, and power resources are extremely expensive
Solution Approach 1:
The patent performs preliminary assessment of bit reliability by evaluating the voltage offset of each bit cell before full deployment. This preliminary action identifies and selects only those bits with sufficiently large offsets (greater than approximately 2 times the RMS noise voltage), eliminating the need for repeated reads during operation and reducing area overhead.
Solution Approach 2:
The patent changes the operating voltage parameter by applying a precharge voltage to the bit lines that compensates for drift in the latch trip point. This parameter adjustment ensures that the read operation occurs at optimal voltage conditions, reducing sensitivity to voltage, temperature, and aging variations without requiring additional circuit area.
3Area of moving object
If bits with small trip points are included to maintain randomness, then area is preserved, but error rates remain high despite filtering
Solution Approach 1:
The patent applies parameter changes by adjusting the precharge voltage level to compensate for drift in the latch trip point. This allows bits with small trip points to be used while maintaining low error rates, as the precharge voltage dynamically offsets the drift caused by voltage, temperature, and aging changes.
Data Source
AI summary
A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.