SRAM PUF Sector Standby Using Metastable Cell Initialization
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Solution Overview
Problem
SRAM memory cells are susceptible to NBTI (Negative-Bias Temperature Instability), which affects the VTP1/VTP2 ratio, leading to instability in stored data and potential data retrieval, especially when used for PUFs, and existing solutions like bit inversion techniques increase power consumption and modify cell structure.
Innovation Solution
A static random access memory device with a control circuit that places a subset of cells into a metastable state by equalizing or disconnecting their nodes and power supply, preventing NBTI effects and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit inversion techniques are used to counteract NBTI effects, then SRAM cell stability is improved, but power consumption increases and access time is degraded
Solution Approach 1:
The patent applies preliminary action by placing SRAM cells into a metastable state before normal operation begins. During power-up, cells are initialized to a metastable condition where both storage nodes are at equal potentials, preventing the development of NBTI effects before they can cause degradation. This proactive approach avoids the need for continuous bit inversion operations that would consume additional power.
Solution Approach 2:
The patent changes the operating parameter of SRAM cells from a stable determined state to a metastable state. By controlling the potentials of storage nodes to be equal or substantially equal during a standby period, the cells operate in a different regime that prevents NBTI-induced threshold voltage drift, thereby improving long-term stability without requiring active intervention.
2Reliability
If periodic bit inversion is performed to limit NBTI degradation, then temporal stability of PUF is improved, but system access time is increased
Solution Approach 1:
The system performs preliminary action by establishing cells in a metastable state during power-up initialization. This one-time setup prevents NBTI degradation from occurring in the first place, eliminating the need for periodic bit inversion operations that would introduce access time penalties during normal PUF operation.
Solution Approach 2:
Instead of inverting bits periodically to counteract degradation, the patent inverts the approach by placing cells in a metastable state where degradation is prevented from occurring. This reverse strategy achieves the same goal of maintaining stability without the time-consuming periodic interventions.
3Reliability
If extra transistors are added to implement bit inversion, then NBTI effects are mitigated, but device complexity increases
Solution Approach 1:
The patent extracts the need for additional transistors by utilizing the existing SRAM cell structure and control circuitry to achieve metastable state initialization. The solution removes the requirement for extra hardware components by cleverly controlling the power-up sequence and node potentials using available circuit elements.
Solution Approach 2:
The control circuit is designed to serve multiple functions: it initializes cells to metastable states, manages power-up sequences, and maintains normal operation modes. This multi-functional approach eliminates the need for dedicated additional transistors or separate circuitry specifically for NBTI mitigation.
4Ease of operation
If cells are kept in determined state for normal operation, then data accessibility is improved, but NBTI-induced data imprint effect occurs
Solution Approach 1:
The patent segments the operational states of SRAM cells into distinct phases: a metastable standby state during power-up and initialization, and a determined operational state during normal data access. This temporal segmentation allows cells to spend most time in the protective metastable state while still enabling full functionality when needed.
Solution Approach 2:
The system performs preliminary action by establishing the metastable state before normal operation begins. This initial configuration prevents data imprint effects from developing during extended periods, while still allowing cells to be accessed normally when required by controlling the duration and conditions of metastable state maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The metastable state prevents NBTI-induced drift in initialisation states, ensuring long-term stability and security of PUFs without increasing power consumption or modifying cell structure.
Implementation Method 1
place the array into a first operating mode in which a first set of cells located in a first zone of the array is in a so-called 'metastable' undetermined state for which their respective first storage node and second storage node are placed at equal or substantially equal potentials
Implementation Method 2
Transistors using PMOS technology are subject to a physical phenomenon referred to as NBTI (Negative-Bias Temperature Instability), which has the effect of increasing their threshold voltage
Data Source
AI summary
A static random access memory device comprising a memory array provided with SRAM memory cells, each of said cells in said array comprising a first storage node and a second storage node, the device further being provided with a control circuit for controlling said cells configured to, after powering up the array, place the array into a first operating mode in which a first set of cells located in a first zone of the array into a so-called “metastable” state for which the first storage node and said second storage node are placed to equal or substantially equal potentials while a second set of cells located in a second zone of the array distinct from the first zone have their respective first node and second node to respective different potentials and corresponding to a given logic state between a low state and a high state and to a logic state complementary to said given state.


