SRAM PUF I/O Circuit Pre-Charging for Stable Responses
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Solution Overview
Problem
Manufacturing variations in integrated circuits lead to instability in PUF responses due to variations in electrical properties, which are exacerbated by input/output (I/O) circuits, necessitating a new I/O circuit design to maintain stability and improve the number of stable bit cells in PUF generators.
Innovation Solution
The development of an I/O circuit that minimizes voltage degradation and maintains stability by equalizing voltage levels between bit cells using pre-charge and pre-discharge units, equalizer circuits, and sense amplifiers, reducing the impact of manufacturing variations on PUF responses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional I/O circuits are used to access bit cells, then the PUF generator can be manufactured with standard processes, but voltage degradation and time delays are introduced that reduce response stability
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to a predetermined voltage level before the PUF challenge is evaluated. This pre-charge operation compensates for voltage degradation that would otherwise occur during the challenge evaluation, ensuring stable voltage levels across all bit cells regardless of manufacturing variations. The pre-charge unit activates before the sense amplifier reads the bit cell states, establishing a consistent starting condition that eliminates voltage-related instability.
2Reliability
If manufacturing variations are present in bit cells, then device diversity for unique PUF responses is achieved, but electrical property variations cause response instability
Solution Approach 1:
The patent implements equipotentiality by ensuring all bit lines are pre-charged to the same predetermined voltage level before challenge evaluation. This equalizes the electrical potential across all bit cells, compensating for manufacturing variations in transistor characteristics, wire resistance, and capacitance. By starting all bit cells at the same voltage potential, the system ensures that manufacturing variations produce consistent relative differences rather than absolute instability, enabling reliable PUF responses despite process variations.
3Reliability
If standard I/O circuits are used, then manufacturing simplicity is maintained, but voltage levels between bit cells become unequal causing instability
Solution Approach 1:
The patent applies preliminary action by incorporating a pre-charge unit that activates before the sense amplifier operation. This pre-charge unit equalizes voltage levels across all bit lines by charging them to a predetermined voltage level, ensuring consistent starting conditions for all bit cells. This preliminary voltage equalization step is integrated into the existing I/O circuit structure, maintaining ease of manufacture while significantly improving voltage consistency and response stability.
4Reliability
If I/O circuits access bit cells without pre-charge, then circuit operation speed is maintained, but voltage degradation causes time delays and instability
Solution Approach 1:
The patent applies preliminary action by performing the pre-charge operation immediately before the sense amplifier reads the bit cell states. This timing ensures that voltage levels are equalized at the critical moment when the challenge is evaluated, minimizing the window for voltage degradation to occur. The pre-charge signal is generated and applied just-in-time, adding minimal overhead to the overall challenge evaluation time while ensuring stable voltage levels throughout the critical measurement period.
Data Source
AI summary
Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.