SRAM PUF Reset Circuit for Voltage Tampering Protection
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Solution Overview
Problem
Existing methods for preventing cell retention failure attacks in SRAM-based PUF generators are either costly, increase boot time, or require complex cryptographic primitives that are beyond the capabilities of resource-constrained devices.
Innovation Solution
A novel circuit is introduced in a memory array to protect PUF generators from cell retention failure attacks by including a reset circuit that sets bit cells to their initial logical states upon detection of a supply voltage tempering event.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate SRAM block is used just for building the PUF, then security against cell retention failure attacks is improved, but implementation costs significantly increase
Solution Approach 1:
The patent merges the PUF generation function with the existing SRAM memory block by adding a voltage tempering detector and reset circuit to the same SRAM block used for data storage. This eliminates the need for a separate dedicated PUF SRAM block, thereby maintaining security while reducing implementation costs and device complexity.
Solution Approach 2:
The SRAM block is designed to serve dual purposes: storing user data during normal operation and generating PUF responses when voltage tempering is detected. The voltage tempering detector and reset circuit enable the same hardware resources to fulfill multiple security and storage functions, avoiding the need for additional dedicated hardware.
2Reliability
If the device waits for stored memory values to decay before reading data after power tempering detection, then security is improved, but boot time significantly increases
Solution Approach 1:
The patent implements a voltage tempering detector that continuously monitors supply voltage and proactively detects tempering events before they can compromise PUF response integrity. Upon detection, the reset circuit immediately resets affected SRAM cells to their initial states, eliminating the need to wait for natural decay and thus preventing boot time delays while maintaining security.
Solution Approach 2:
The voltage tempering detector provides real-time feedback about supply voltage conditions to the reset circuit. This feedback mechanism enables the system to respond immediately to voltage tempering events by resetting cells before they can be exploited, thereby maintaining both security and fast boot times without requiring time-based waiting periods.
3Reliability
If cryptographic primitives are used to obfuscate PUF response bits, then security is improved, but device complexity exceeds capabilities of resource-constrained devices
Solution Approach 1:
The patent employs a physical self-service mechanism where voltage tempering naturally causes SRAM cells to lose their stored values and revert to predetermined initial states. The voltage tempering detector and reset circuit exploit this physical behavior to generate secure PUF responses without requiring complex cryptographic algorithms, making the solution suitable for resource-constrained devices while maintaining strong security.
Solution Approach 2:
The patent converts the harmful effect of voltage tempering (which causes data loss in SRAM cells) into a beneficial security feature. By detecting voltage tempering and using it to force cells into known initial states, the system transforms a potential attack vector into a reliable mechanism for generating secure PUF responses without complex cryptography.
Data Source
AI summary
Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.