SRAM PUF Generation via Voltage-Induced Bit Cell Instability

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Solution Overview

Problem

Conventional Static Random Access Memory (SRAM) Physically Unclonable Functions (PUFs) are considered weak due to limited and unsophisticated challenges, making them vulnerable to replication by attackers, and existing techniques require additional hardware or are susceptible to delayering and probing attacks.

Innovation Solution

The method induces instability in SRAM bit cells by altering the supply voltage, using bit cell read failures to generate a strong PUF with multiple challenges and unique responses, increasing the difficulty of replication and resistance to attacks like delayering and probing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional SRAM PUF techniques are used, then the implementation is simple, but the security strength is weak and vulnerable to replication

Engineering Contradiction:
ImprovePUF security strengthVSAvoidchallenge-response complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the operational parameters of SRAM bit cells by applying voltages outside the normal operating range (e.g., -0.7V to 1.2V) to induce instability and create diverse read failure patterns. This transforms the PUF from a weak conventional system to a strong system with multiple challenge types, resolving the contradiction between security strength and implementation simplicity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic voltage sequencing where voltages are applied in specific sequences (e.g., V1 then V2, or V2 then V1) to create time-dependent challenge-response pairs. This dynamic approach multiplies the challenge space without requiring additional hardware, strengthening security while maintaining implementation feasibility

Inventive Principle:
Principle #15Dynamics

2Reliability

If additional hardware is added to strengthen PUF, then security improves, but device complexity and cost increase

Engineering Contradiction:
ImprovePUF security strengthVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the existing SRAM memory array perform multiple functions: normal memory operation and PUF generation. By using the same hardware infrastructure for both purposes, the patent strengthens security without adding dedicated PUF hardware, resolving the contradiction between security and hardware complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent exploits the inherent physical variations and instability characteristics of the SRAM bit cells themselves to generate the PUF effect. The SRAM structure serves its own PUF function through controlled voltage stress, eliminating the need for separate PUF hardware components

Inventive Principle:
Principle #25Self-service

3Reliability

If conventional PUF challenges are used, then the operation is simple, but the PUF is susceptible to delayering and probing attacks

Engineering Contradiction:
Improveattack resistanceVSAvoidchallenge application complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent applies periodic voltage sequences in different orders (V1-V2, V2-V1, V1-V2-V3, etc.) to create multiple challenge types. This periodic variation in voltage application makes the PUF resistant to static analysis attacks like delayering and probing, while maintaining operational simplicity through systematic voltage sequencing

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12050495B2Methods and apparatus to create a physically unclonable function
Publication Date: 2024.07.30 TEXAS INSTRUMENTS INC
  • US12050495B2 patent drawing
  • US12050495B2 patent drawing
  • US12050495B2 patent drawing

AI summary

Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.