SRAM Cell With Separate Read Access Circuit
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Solution Overview
Problem
The stability of static memory cells, particularly in SRAM arrays, is compromised as integrated circuit technologies scale due to threshold voltage variations, leading to potential failures in 6-T memory cells, and existing solutions like the 8-T architecture require additional power and peripheral circuitry for voltage management.
Innovation Solution
A memory array system with memory cells operating at reduced voltages during both functional operations and stand-by mode, utilizing a separate read access circuit and write access circuit, where the reduced voltage is derived from the difference between array supply voltages and peripheral supply voltages, allowing for efficient power management and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional 6-T memory cell architecture is used, then compact structure is achieved, but stability fails due to threshold voltage variations
Solution Approach 1:
The patent divides the memory cell into two separate functional blocks: a storage element (flip-flop) and a read assist circuit. This segmentation allows the storage element to maintain data while the read assist circuit handles read operations, eliminating read disturbs and improving stability without increasing overall cell area significantly.
Solution Approach 2:
The patent introduces a read assist circuit as an intermediary between the storage element and the read bit line. This intermediary circuit buffers the read operation, preventing direct disturbance to the stored data while still enabling successful read operations through controlled coupling during read cycles.
2Reliability
If 8-T architecture with read assist circuit is used, then read disturbs are eliminated, but power consumption increases
Solution Approach 1:
The patent employs dynamic voltage scaling by operating the storage element at a reduced voltage (VDD_REDUCED) during stand-by mode and switching to full voltage (VDD) during active read/write operations. This dynamic voltage adjustment significantly reduces power consumption during idle periods while maintaining full functionality during active operations.
Solution Approach 2:
The patent changes the operating voltage parameter of the storage element based on operational state. By using a reduced voltage (VDD_REDUCED) during stand-by mode and switching to full voltage (VDD) during active operations, the patent reduces power consumption while maintaining full functionality during active operations.
3Use of energy by moving object
If voltage is reduced for power savings, then power consumption decreases, but operational reliability may be compromised
Solution Approach 1:
The patent employs dynamic voltage scaling by operating the storage element at a reduced voltage (VDD_REDUCED) during stand-by mode and switching to full voltage (VDD) during active read/write operations. This dynamic voltage adjustment significantly reduces power consumption during idle periods while maintaining full functionality during active operations.
Solution Approach 2:
The patent performs preliminary voltage adjustment by switching the storage element to full voltage (VDD) before active operations and back to reduced voltage (VDD_REDUCED) after operations complete. This preliminary action ensures that the storage element is properly voltage-conditioned for reliable operation before data operations occur.
Data Source
AI summary
A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.