SRAM Read Assist Unit Suppresses Word Line Voltage
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, decreasing operating voltages affect IC performance, particularly in static random access memory (SRAM) devices, where existing technologies struggle to maintain effective data storage and retrieval operations.
Innovation Solution
The implementation of a memory circuit design that includes read assist units, clamping circuits, and bit line control units to manage voltage levels on word lines and bit lines, employing NMOS and PMOS transistors to suppress word line voltages during read operations and equalize bit line/bar voltages, thereby improving static noise margin (SNM) and reducing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operating voltage is decreased to reduce power consumption, then energy efficiency is improved, but static noise margin and data storage reliability deteriorate
Solution Approach 1:
The clamping circuit performs preliminary action by clamping the bit line voltage to a first intermediate voltage level before the read operation completes. This preliminary voltage adjustment ensures that the bit line voltage is optimized for the subsequent write operation, maintaining reliable data storage even at lower operating voltages. The read assist unit also performs preliminary action by suppressing the word line voltage during read operations to improve signal integrity before write operations occur.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting voltage levels on bit lines and word lines during different operations. The clamping circuit changes the bit line voltage parameter to a first intermediate voltage level during write operations, while the read assist unit suppresses word line voltage during read operations. These parameter adjustments enable the SRAM to maintain reliable operation across a range of operating voltages while reducing power consumption.
2Reliability
If word line voltage is suppressed during read operations to improve signal integrity, then static noise margin is improved, but energy consumption increases
Solution Approach 1:
The read assist unit performs preliminary action by suppressing the word line voltage during read operations before write operations occur. This preliminary voltage suppression improves signal integrity and static noise margin by ensuring that the word line voltage is optimized for the upcoming write operation. The clamping circuit also performs preliminary action by clamping the bit line voltage before the write operation, further preparing the circuit for efficient and reliable operation.
3Reliability
If bit line voltage is equalized before write operation to improve data storage reliability, then static noise margin is improved, but energy consumption increases
Solution Approach 1:
The clamping circuit performs preliminary action by clamping the bit line voltage to a first intermediate voltage level before the write operation completes. This preliminary voltage adjustment ensures that the bit line voltage is optimized for the subsequent write operation, maintaining reliable data storage even at lower operating voltages. The read assist unit also performs preliminary action by suppressing the word line voltage during read operations to improve signal integrity before write operations occur.
Data Source
AI summary
A static random access memory (SRAM) including at least a memory cell array, a first data line connected to the memory cell array, and a read assist unit connected to the first data line. The read assist unit is configured to suppress a voltage level of the first data line during a read operation of the memory cell array.