SRAM Memory Cell Read Circuit for Low-Leakage Data Integrity
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Solution Overview
Problem
Read disturb errors occur in static random access memory (SRAM) cells due to signal leakage during data reading, causing data stored in the cells to change.
Innovation Solution
A memory cell design incorporating a dedicated read circuit with a pair of series-connected transistors and a word read line, allowing independent read and write operations, and utilizing cascoded transistors to reduce signal leakage and static power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is read from an SRAM memory cell, then the stored data can be accessed, but signal leakage occurs causing read disturb errors and data change
Solution Approach 1:
The patent divides the memory cell into separate read and write circuits with independent transistor pathways. The read circuit uses dedicated read transistors (e.g., first and second read transistors) that are spatially and functionally separated from the write passgate transistors, preventing signal leakage between circuits while maintaining data integrity during read operations.
Solution Approach 2:
The patent introduces intermediate nodes (e.g., first intermediate node, second intermediate node) that act as buffers between the storage nodes and the read/write circuits. These intermediate nodes isolate the storage nodes from direct connection during read operations, preventing signal leakage while enabling data access through controlled signal transmission.
2Reliability
If a dedicated read circuit is added to the memory cell, then read disturb errors are reduced and independent read/write operations are enabled, but the device complexity increases
Solution Approach 1:
The patent designs the read circuit transistors to serve multiple functions: they act as read access transistors during read operations, and as protective isolation elements during write operations. This multi-functionality reduces the need for completely separate transistor sets, thereby limiting the increase in device complexity while achieving reliable independent read/write operations.
Solution Approach 2:
The patent combines the read circuit and write circuit within the same memory cell structure, sharing common storage nodes and voltage rails while maintaining separate transistor pathways. This integration approach reduces overall device complexity compared to completely separate read and write memory cells, while still enabling independent operations and reducing read disturb errors.
Data Source
AI summary
A memory cell may include a word write line, a first bit line, a first storage node, a second storage node, a first passgate transistor, and a read circuit. A gate of the first passgate transistor may be electrically connected to the word write line. A source of the first passgate transistor may be electrically connected to the first bit line. A drain of the first passgate transistor may be electrically connected to one of the first and second storage nodes. The read circuit may include a word read line, a first read transistor, and a second read transistor. A gate of the first read transistor may be electrically connected to the first storage node. A gate of the second read transistor may be electrically connected to the word read line. A drain of the first read transistor may be electrically connected to the second read transistor.