SRAM Read Current Testing via Bit Line Coupling
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Solution Overview
Problem
Current testing methods for reading current in static random access memory (SRAM) are complex, require numerous hardware devices, and are not suitable for batch testing due to the need for multiple leads and prolonged testing times.
Innovation Solution
A simplified testing method that involves coupling the gate of pull-down transistors to bit lines, setting word lines and bit lines at high potentials, and sensing current, reducing the number of hardware interfaces and streamlining the testing process to enable efficient batch testing of SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional voltage test-based testing method is used, then testing coverage is limited, but testing simplicity is maintained
Solution Approach 1:
The patent replaces traditional voltage-based testing with current-based testing. By measuring the current flowing through the bit lines during read operations, the method detects memory cell abnormalities more effectively. This substitution of testing paradigm (from voltage to current measurement) improves fault coverage while maintaining relative simplicity through direct current sensing at existing bit line interfaces.
2Reliability
If current testing method with multiple leads is used, then fault detection capability is improved, but testing time increases
Solution Approach 1:
The patent merges the current sensing function into the existing bit line structure. By using the same bit lines that carry data signals also as current sensing paths, the method eliminates the need for separate dedicated sensing leads. This consolidation allows current measurement to be performed concurrently with normal read operations, improving fault detection without adding significant testing time.
Solution Approach 2:
The bit lines serve dual functions: they carry data signals for normal memory operations and simultaneously function as current sensing paths for testing. This multi-functionality reduces the need for additional dedicated testing hardware and allows testing to be integrated into the normal operation flow, reducing overall testing time while maintaining detection capability.
3Measurement precision
If comprehensive current measurement is performed, then measurement precision is improved, but hardware requirements increase
Solution Approach 1:
The patent extracts the current measurement function from complex multi-lead hardware configurations and concentrates it into simple current sensing at the bit line interfaces. By focusing measurement on the essential current flow paths (the bit lines), the method achieves sufficient measurement precision without requiring comprehensive multi-point measurements, thereby reducing hardware complexity.
Data Source
AI summary
The present disclosure provides a testing method for reading current of static random access memory, the method comprising: for each basic static random access memory cell, coupling a gate of a first pull-down transistor to a first bit line; setting a word line and the first bit line at a high potential; and sensing current of the first bit line. The testing method provided in the present disclosure can also be applied to static random access memory cells arranged in matrices, so as to efficiently complete the tests for the reading current of the static random access memory in batches.