SRAM Read-Modify-Write Single Clock Cycle Internal Modification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing SRAM circuit for performing read-modify-write operations requires multiple clock cycles, leading to high power consumption due to data signal toggling, especially since the mathematical modify operation is performed externally.
Innovation Solution
The SRAM circuit is redesigned to perform the read, modify, and write operations within a single clock cycle by integrating the data modification circuit internally, eliminating the need for external data calculation and reducing power consumption through internal data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the mathematical modify operation is performed externally to the SRAM, then the SRAM structure remains simple, but the power consumption increases due to data signal toggling across multiple clock cycles
Solution Approach 1:
The patent merges the external data modification circuit with the internal SRAM structure by providing a dual-port memory array where one port is coupled to the data input and another port is coupled to the data output. This allows the modify operation to occur internally within the same clock cycle as the read and write operations, eliminating the need for external modification circuits and reducing power consumption from data signal toggling.
2Ease of manufacture
If the read-modify-write operation is performed in multiple clock cycles, then the operation can be completed with external modification circuitry, but the operation time increases and power consumption increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the dual-port memory array structure before operation, allowing the modify operation to be performed concurrently with read and write operations in the same clock cycle. The first port receives modified data while the second port simultaneously outputs original data, eliminating the need for sequential multi-cycle operations.
3Device complexity
If data modification is performed externally, then the SRAM can use a simpler single-port structure, but data signal toggling increases power consumption
Solution Approach 1:
The patent introduces an intermediary dual-port memory structure that mediates between the data input and data output ports. The first port (data input) receives modified data from external circuits, while the second port (data output) simultaneously outputs original data to external modification circuits. This intermediary structure allows both ports to remain active within the same clock cycle, reducing data signal toggling and power consumption.
Data Source
AI summary
A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.