SRAM Read Stack Threshold Voltage Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM cells with additional read stacks face challenges in achieving high read performance while minimizing leakage current, as enhancing pull-down capability often results in increased leakage or variability, and existing methods for adjusting threshold voltages come with drawbacks such as larger cell size or increased complexity.
Innovation Solution
The integration of SRAM cells with read stacks featuring a read pull-down transistor and a read pass gate transistor, where the read pull-down transistor has a lower threshold voltage than the read pass gate transistor, optimizing performance without increasing leakage current and maintaining existing fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel width is increased to enhance pull-down capability, then read performance is improved, but the SRAM cell size increases
Solution Approach 1:
The patent changes the threshold voltage parameter of the read pull-down transistor by adjusting conductivity-determining impurity ion concentration or type, enabling enhanced pull-down capability without increasing channel width, thus improving read performance while maintaining compact cell size
2Productivity
If the channel length is decreased to enhance pull-down capability, then read performance is improved, but device variability and leakage current increase
Solution Approach 1:
The patent changes the threshold voltage parameter of the read pull-down transistor through conductivity-determining impurity adjustments, enabling enhanced pull-down capability without reducing channel length, thus improving read performance while maintaining low leakage current and device reliability
3Productivity
If the threshold voltage of the read stack is reduced to increase pull-down capability, then read performance is improved, but leakage current increases
Solution Approach 1:
The patent applies different threshold voltage characteristics to different transistors within the read stack: the read pull-down transistor has conductivity-determining impurities configured for low threshold voltage to maximize pull-down capability, while the read pass gate transistor has different impurity configuration for higher threshold voltage to minimize leakage current, achieving both high read performance and low leakage through localized property differentiation
Solution Approach 2:
The patent changes the threshold voltage parameter of the read pull-down transistor specifically (not the entire read stack) by adjusting conductivity-determining impurity concentration or type, enabling enhanced pull-down capability while the read pass gate transistor maintains higher threshold voltage to keep leakage current low
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances read performance by about 14% while maintaining low leakage current, achieved through selective threshold voltage adjustments using conductivity-determining impurity ions, without adding additional fabrication steps or complexity.
Implementation Method 1
selective threshold voltage adjustment using conductivity-determining impurity ions
Data Source
AI summary
Integrated circuits that include SRAM cells having additional read stacks are provided. In accordance with one embodiment an integrated circuit includes a memory storage array of memory cells. The integrated circuit includes a read stack coupled to each memory cell of the memory storage array. Each read stack includes a read pull-down transistor having a first threshold voltage, and a read pass gate transistor coupled in series with the read pull down transistor and having a second threshold voltage greater than the first threshold voltage.