SRAM Read Timing Control With Local Read Enable Circuits
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Solution Overview
Problem
Existing SRAM circuits face performance limitations due to extended connection lines causing contention between read enable and sense enable signals, leading to reduced performance and inefficiencies in read operations.
Innovation Solution
Implementing local read enable control circuits within memory banks, coupled with a global control circuit, to optimize time margins between read and sense operations, ensuring adequate timing for bit line stability and sense amplifier operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If connection lines are extended to accommodate higher integration density, then more components can be integrated into a given area, but signal contention occurs between read enable and sense enable signals leading to reduced performance
Solution Approach 1:
The patent segments the read enable control into local and global components. Local read enable control circuits are distributed within memory banks while a global read enable control circuit coordinates overall timing. This segmentation allows independent optimization of local timing margins without affecting entire system timing, resolving the signal contention issue while maintaining high integration density
Solution Approach 2:
The patent implements preliminary action by asserting the sense enable control signal in accordance with a clock signal transition edge before the actual sense operation. This preliminary assertion ensures that sense amplifiers are prepared and stable before read operations begin, preventing signal contention and ensuring reliable operation at high integration densities
2Loss of time
If local read enable control circuits are implemented within memory banks, then time margins for read and sense operations are optimized, but device complexity increases
Solution Approach 1:
The patent merges the local read enable control circuit with the existing memory bank structure, integrating timing control functionality directly into the memory bank rather than as a separate external component. This merging optimizes time margins by reducing signal path length while minimizing the increase in device complexity through shared infrastructure
Solution Approach 2:
The global read enable control circuit serves multiple functions: it generates the read enable signal, coordinates with sense enable control signals, and manages timing margins across all memory banks. This multi-functionality reduces the need for separate dedicated circuits, optimizing time margins without proportionally increasing device complexity
Data Source
AI summary
A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.