SRAM Read Circuit with Twist Circuit for Data Security

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Solution Overview

Problem

Existing SRAM memory technologies face challenges in securing data against unauthorized access through electrical probing, as the current consumption patterns for reading '0' and '1' bits can be distinguished, potentially allowing hackers to reverse-engineer the data.

Innovation Solution

The implementation of a dual-memory array system with a read circuit that includes a twist circuit and a random number generator, which simultaneously reads data from both arrays and randomly swaps the signals to the sense amplifiers, ensuring that the current consumption patterns for reading '0' and '1' bits are identical.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional SRAM reading method is used, then data can be read from memory, but current consumption patterns reveal data values allowing electrical probing attacks

Engineering Contradiction:
Improvedata securityVSAvoiddistinguishable current consumption patterns
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the current consumption parameter by introducing dummy read operations and random signal swapping. The sense amplifiers are forced to consume identical current regardless of the actual data value by reading complementary data from auxiliary arrays and randomly exchanging signal paths, making current consumption independent of the stored bit value.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces auxiliary memory arrays and twist circuits as intermediaries between the main memory array and the sense amplifiers. These intermediaries enable the system to read dummy data and swap signals randomly, preventing direct correlation between current consumption and actual data values while still allowing legitimate data access.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dual-memory array system with twist circuit is implemented, then data security against electrical probing is improved, but device complexity increases

Engineering Contradiction:
Improvedata securityVSAvoidmemory array structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory system into main arrays and auxiliary arrays, with the main arrays storing actual data and the auxiliary arrays storing complementary or dummy data. This segmentation allows the system to perform secure read operations by selectively accessing different arrays and swapping their outputs, achieving security without completely redesigning the entire memory structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The auxiliary memory arrays serve multiple functions: they store dummy data for security operations, provide complementary data for swapping operations, and can potentially be used for additional storage capacity. This multi-functionality justifies the added complexity by providing both security benefits and potential performance improvements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12243586B2Method for reading memory
Publication Date: 2025.03.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12243586B2 patent drawing
  • US12243586B2 patent drawing
  • US12243586B2 patent drawing

AI summary

Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.