SRAM Read/Write Timing Control for Weak-Transistor Reliability
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Solution Overview
Problem
The write and read operations in static random access memory (SRAM) cells are limited by the strength of critical transistors, leading to unbalanced cycle times and potential performance issues, particularly in worst-case scenarios where the pull-up or pull-down transistors are weak, affecting the frequency and stability of data storage.
Innovation Solution
A memory circuit design that includes a control circuit with multiple delay circuits and multiplexers to generate delayed word line signals, allowing for adjustable cycle times based on operational mode selection, optimizing write performance by sacrificing read performance in a balanced speed mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory circuit uses standard delay timing for both read and write operations, then the circuit design is simple, but the write operation cannot ensure sufficient voltage levels on storage nodes when pull-up transistors are weak, leading to unreliable data storage
Solution Approach 1:
The patent implements dynamic timing adjustment by using a mode control signal to selectively activate different delay circuit paths. When in write mode, a first delay circuit provides extended delay timing to ensure weak pull-up transistors can reach sufficient voltage levels. When in read mode, a second delay circuit provides standard timing. This dynamic adaptation resolves the contradiction by making the timing behavior flexible rather than fixed, ensuring reliability when needed without permanently increasing complexity.
Solution Approach 2:
The patent changes the time parameter of the delay circuit based on operational mode. By using multiplexers to select between different delay circuit implementations (first delay circuit with longer delay for write, second delay circuit with standard delay for read), the effective delay parameter is adjusted according to the specific operation requirements. This parameter change allows the system to achieve reliable write operations without sacrificing read performance or maintaining unnecessary complexity in all operations.
2Reliability
If the memory circuit extends the write cycle time to accommodate weak pull-up transistors, then write reliability improves, but read operation frequency decreases due to unbalanced cycle times
Solution Approach 1:
The patent makes the cycle time dynamic by using the mode control signal to select between different delay configurations. During write operations, the first delay circuit extends the cycle time to ensure reliable data storage even with weak pull-up transistors. During read operations, the second delay circuit restores standard timing, maintaining high read frequency. This dynamic timing adjustment resolves the contradiction by applying extended timing only when necessary for write reliability.
Solution Approach 2:
The patent segments the delay functionality into separate first and second delay circuits, each optimized for specific operational modes. The first delay circuit handles write operations with extended timing, while the second delay circuit handles read operations with standard timing. This segmentation allows independent optimization of each operation type, ensuring write reliability without compromising read frequency performance.
3Reliability
If the memory circuit uses standard delay circuits, then the circuit area is minimized, but it cannot provide sufficient delay variation to handle worst-case transistor strength variations
Solution Approach 1:
The patent implements dynamic selection between different delay circuit configurations using mode control signals and multiplexers. The first delay circuit provides extended delay for worst-case write scenarios, while the second delay circuit provides standard delay for normal operations. By dynamically selecting which delay circuit to use based on operational mode rather than always using the more complex first delay circuit, the system achieves worst-case reliability when needed while minimizing average area usage.
Solution Approach 2:
The patent applies different delay characteristics to different operational modes locally. The first delay circuit with extended timing is activated only during write operations where it is needed, while the second delay circuit with standard timing is used during read operations. This local application of enhanced delay characteristics ensures worst-case reliability for write operations without unnecessarily increasing the area of the control circuit for all operations.
Data Source
AI summary
A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.