Single-Ended SRAM Reading Circuit Clock Simplification
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Solution Overview
Problem
Conventional single-ended reading circuits for SRAM suffer from high power consumption, many output glitches, and low reliability due to their design requirements of using both pre-charging and reading clocks.
Innovation Solution
A single-ended reading circuit design that includes a pre-charger, high-level maintainer, NAND gates, and an output driver, utilizing P-type transistors and an inverter, which operates solely with a pre-charging clock to selectively pull up the bit-line voltage, eliminating the need for a reading clock and optimizing transistor capabilities for reduced power consumption and increased reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-ended reading circuits use both pre-charging clock and reading clock, then the reading operation can be performed, but power consumption increases and output glitches occur
Solution Approach 1:
The patent extracts and removes the reading clock signal from the conventional reading circuit, retaining only the pre-charging clock signal. This simplification eliminates the complexity of coordinating multiple clock signals and reduces power consumption while maintaining reading functionality through the modified latch circuit design.
Solution Approach 2:
The patent inverts the traditional approach by using the pre-charging clock signal for both pre-charging and reading operations. Instead of using separate clocks for these functions, the invention repurposes the pre-charging clock to control the reading process, thereby reducing power consumption and eliminating output glitches associated with multiple clock signals.
2Ease of operation
If conventional reading circuits use multiple clock signals, then reading operation is enabled, but circuit complexity and number of components increase
Solution Approach 1:
The patent extracts and removes the reading clock signal from the conventional reading circuit, retaining only the pre-charging clock signal. This simplification eliminates the complexity of coordinating multiple clock signals and reduces power consumption while maintaining reading functionality through the modified latch circuit design.
Solution Approach 2:
The pre-charging clock signal is designed to perform multiple functions: it controls both the pre-charging operation and the reading operation. This multi-functionality reduces the need for separate clock signals and simplifies the overall circuit structure while maintaining full operational capability.
3Speed
If conventional reading circuits operate with standard transistor configuration, then circuit implementation is straightforward, but operation speed is limited
Solution Approach 1:
The patent optimizes the transistor parameters, specifically the width-to-length ratios of the NMOS and PMOS transistors in the latch circuit. By adjusting these parameters, the circuit achieves faster switching speeds and improved operation performance while remaining compatible with standard manufacturing processes.
Data Source
AI summary
A single-ended reading circuit includes a pre-charger, a high-level maintainer, a first NAND gate, a second NAND gate, a third NAND gate, and an output driver. The first NAND gate has a first input terminal for receiving a pre-charging clock, a second input terminal coupled to a first node, and an output terminal coupled to a second node. The second NAND gate has a first input terminal coupled through a third node to the second node, a second input terminal coupled to a fourth node, and an output terminal coupled to a fifth node. The third NAND gate has a first input terminal coupled to the fifth node, a second input terminal coupled to the first node, and an output terminal coupled to the fourth node.