SRAM Cell Area Reduction via Recessed Gate Line
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Solution Overview
Problem
Conventional static random access memory (SRAM) cells occupy a relatively large area, limiting the integration density and efficiency of memory devices.
Innovation Solution
The design incorporates a recessed gate line as the gate of pass-gate transistors, reducing the gate size and distance between the gate and adjacent interconnect components, along with slit contacts for electrical connections, to minimize the size of the SRAM cell while allowing for independent control of pass-gate and pull-down transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional SRAM cell structure is used, then transistor control is achieved, but cell area is large
Solution Approach 1:
The gate line transitions from a planar two-dimensional structure to a three-dimensional recessed structure that extends vertically into the substrate. This dimensional change allows the gate to control multiple strip doped regions (first, second, third, and fourth regions) simultaneously at different depths, achieving reliable transistor control while reducing the horizontal footprint of the SRAM cell
Solution Approach 2:
The SRAM cell is segmented into multiple discrete strip doped regions (first, second, third, and fourth regions) arranged in a sequence. The recessed gate line selectively controls these segmented regions, allowing independent control of pass-gate transistors and pull-down transistors. This segmentation enables compact layout while maintaining functional reliability
2Area of moving object
If gate size is reduced, then SRAM cell size decreases, but manufacturing precision becomes more difficult
Solution Approach 1:
By moving the gate control function to a recessed three-dimensional structure, the horizontal dimensions of the gate can be reduced without proportionally reducing the effective gate control area. The vertical extension into the substrate compensates for the reduced horizontal footprint, maintaining manufacturing precision while achieving smaller cell area
Solution Approach 2:
The recessed gate line is nested within the substrate structure, with the gate extending downward into recesses formed in the substrate. This nesting arrangement allows the gate to occupy vertical space rather than horizontal space, enabling compact cell layout while maintaining adequate gate dimensions for manufacturability
Data Source
AI summary
A static random access memory (SRAM) including at least a SRAM cell is provided. A gate layout of the SRAM cell includes first to fourth strip doped regions, a recessed gate line and first and second gate lines. The first to fourth strip doped regions are disposed in the substrate in order and separated from each other. The recessed gate line intersects the first to fourth strip doped regions. The first to fourth strip doped regions are disconnected at intersections with the recessed gate line. The first gate line intersects the first and the second strip doped regions. The first and the second strip doped regions are disconnected at intersections with the first gate line. The second gate line intersects the third the fourth strip doped regions. The third and the fourth strip dopeds region are disconnected at intersections with the second gate line.