SRAM Recovery Circuit for Write Operation Driving Strength
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, decreasing operating voltages affect IC performance, particularly in static random access memory (SRAM) devices, where existing technologies struggle to maintain effective write operations and driving strength during dummy read recovery.
Innovation Solution
Incorporating a recovery circuit within the driver circuit of SRAM, electrically coupled with data lines, which assists in pulling voltage levels to specific logical levels, improving the driving strength and recovery from dummy reads by utilizing NOR gates and transistors to control bit lines and bit line bars during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If operating voltage is decreased to enable smaller and more complex ICs, then IC size and complexity are improved, but driving strength and write operation effectiveness deteriorate
Solution Approach 1:
The driver circuit is segmented into multiple independent pull-up networks, each responsible for specific bit lines. This allows each segment to be optimized for strong driving capability while the overall system maintains compact size through modular architecture.
Solution Approach 2:
The patent combines dummy read functionality and write operation support into a unified driver circuit architecture. The same pull-up networks serve both dummy read recovery and write operation needs, eliminating the need for separate circuits and maintaining compact size while providing strong driving strength.
2Device complexity
If conventional driver circuits are used without recovery circuits, then device complexity is reduced, but recovery from dummy read operations is insufficient
Solution Approach 1:
The pull-up networks are activated in advance during dummy read operations to pre-charge bit lines to appropriate voltage levels. This preliminary action ensures that when write operations commence, the bit lines are already in the correct state for reliable data writing, improving recovery without adding complex recovery circuits.
3Power
If pull-up networks are activated during write operations, then driving strength is improved, but unintended activation during dummy read may occur
Solution Approach 1:
The pull-up networks employ dynamic control through word line signals that enable or disable specific networks based on the current operation type. During dummy read, only the appropriate pull-up network remains active while others are disabled, preventing unintended activation. This dynamic switching maintains strong driving strength when needed while ensuring operational reliability.
Data Source
AI summary
A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.