SRAM Redundancy Schemes for Multiple Row Repair
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Solution Overview
Problem
Conventional semiconductor memory cell arrays with row redundancy can only repair one defective or faulty row of SRAM memory cells, limiting the efficiency of repair for multiple defective rows.
Innovation Solution
Implementing a shift-based redundancy scheme that subdivides the memory cell array into independent sections and portions, allowing for separate wordline driver and row shift circuitry to independently shift defective rows to redundant rows, thereby increasing the repair efficiency of multiple rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If conventional row redundancy layout is used, then one defective row can be repaired, but multiple defective rows cannot be repaired simultaneously
Solution Approach 1:
The memory array is divided into multiple independent sections, each with its own redundant row and wordline driver circuitry. This segmentation allows each section to independently repair defective rows without interfering with other sections, enabling multiple defective rows to be repaired simultaneously across different sections of the array.
Solution Approach 2:
The patent implements dynamic row shifting capability where defective rows can be shifted to redundant rows through controlled wordline switching. The system dynamically reconfigures which rows are active and which are redundant based on defect detection, allowing flexible repair of multiple rows at different times or simultaneously in different sections.
2Reliability
If row redundancy is added to repair defective rows, then repair capability improves, but device complexity increases
Solution Approach 1:
By dividing the memory array into independent sections with separate redundant rows and wordline drivers, the patent localizes the redundancy overhead to only the affected sections rather than requiring full-array redundancy. This reduces the overall complexity compared to conventional approaches while maintaining high repair capability.
Solution Approach 2:
The redundant rows and wordline driver circuitry serve multiple functions: they act as backup storage cells for repair operations, and can also function as regular memory cells when no defects are present. This multi-functionality reduces the net increase in device complexity by maximizing utilization of the added components.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.