SRAM Redundancy Schemes for Zero Address Setup Time Penalty
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Solution Overview
Problem
Conventional SRAM redundancy schemes in SoCs experience increased address setup time due to additional comparison operations, which slows down the overall performance and speed of the system.
Innovation Solution
Implementing a bolt-on row redundancy scheme with zero address setup time penalty, where redundant rows are provided in a separate memory array, allowing for parallel operations and eliminating the need for additional comparison, thereby maintaining performance without increasing setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row redundancy scheme with internal comparator is used, then faulty memory cells can be replaced with redundant cells, but address setup time increases due to additional comparison operations
Solution Approach 1:
The patent divides the memory system into two separate arrays: a main SRAM array for regular operations and a separate redundant memory array for fault replacement. This segmentation allows the redundant array to operate independently without interfering with the timing of the main array, thus eliminating the address setup time penalty while maintaining fault tolerance capability
Solution Approach 2:
The patent extracts the comparison function from the main memory access path by providing pre-decoded row addresses for the redundant array. The redundant array receives its row addresses directly from the decoder without requiring additional comparison operations, effectively removing the time-consuming comparison step from the critical access path
2Reliability
If redundant rows are integrated within the same SRAM array, then fault replacement is achieved, but device complexity increases due to internal comparator and address matching logic
Solution Approach 1:
The patent extracts the comparison logic from the redundant memory access path by providing dedicated row address decoders for both the main and redundant arrays. The redundant array receives pre-selected row addresses directly, eliminating the need for internal comparators and address matching circuits within the SRAM array, thus reducing device complexity
Solution Approach 2:
The patent uses a universal row address decoder that serves both the main SRAM array and the redundant memory array. This single decoder structure provides row addresses to both arrays simultaneously, eliminating the need for separate comparison circuits and reducing overall device complexity while maintaining the ability to replace faulty cells
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first memory cell array disposed in a first area of the integrated circuit. The first memory cell array includes first memory cells. The integrated circuit may include a second memory cell array disposed in a second area of the integrated circuit that is different than the first area. The second memory cell array includes redundant memory cells that are separate from the first memory cells.